參數(shù)資料
型號: S-8328J25MC-F2F-T2
元件分類: 穩(wěn)壓器
英文描述: 0.3 A SWITCHING CONTROLLER, 287.5 kHz SWITCHING FREQ-MAX, PDSO5
封裝: PLASTIC, SOT-23, 5 PIN
文件頁數(shù): 14/65頁
文件大小: 759K
代理商: S-8328J25MC-F2F-T2
SMALL PACKAGE PWM/PFM CONTROL STEP-UP SWITCHING REGULATOR
Rev. 7.2-10
S-8324/8328 Series
Seiko Instruments Inc.
21
4.2. Enhancement MOS FET Type
5. Others (S-8324D/J and S-8328E/J only)
The S-8324D/J and S-8328E/J are applicable to the following uses because the power pin for IC chip and Vout pin for output
voltage are separated:
When changing the output voltage with an external resistance.
When outputing the high voltage such as +12 V or 15 V.
When making the step-down DC/DC converter.
When making the inverted DC/DC converter.
Choose the products in the following table according to applications for
to
.
Use
Step-up
Step-down
Output voltage VCC
2V
≤VCC<3V 3V≤VCC<5V 5V≤VCC<9V
9V
≤VCC
Ref. circuit
2V
≤VCC<3V 3V≤VCC<5V 5V≤VCC<9V
Ref. circuit
S-8324D20
Std. circuit (5)
Appl. circuit 3
S-8324D30
Std. circuit (5)
Appl. circuit 3
S-8324D50
Std. circuit (5)
Appl. circuit 3
S-8324J25
Std. circuit (5)
S-8324J50
Std. circuit (5)
S-8328E20
Std. circuit (6)
S-8328E50
Std. circuit (6)
S-8328J25
Std. circuit (6)
S-8328J50
Std. circuit (6)
Connection to VDD pin
VIN or VCC
VIN
VIN
The operational precautions are follows:
I. This IC starts to oscillate and step up operation at VDD=0.8V(1.3V for J-type) but frequency of the oscillator does not stabilize.
Input the voltage from 2 V to 9 V for VDD pin to get the stabilized output voltage and oscilation frequency.
The input voltage from 2 V to 9 V for VDD pin allows the connection of VDD pin to both input power pin VIN and output power pin
Vout.
II. Choose external resistors RA and RB not to affect to the output voltage with the consideration of the impedance between VOUT
and VSS pins in the IC chip.
Internal resistance between VOUT and VSS pins are as follows:
S-8324D20, S-8324J20, and S-8328E20: 3.0 M
to 19.6 M
S-8324J25, S-8328J25: 3.9 M
to 22.5 M
S-8324D30: 3.3 M
to 22.6 M
S-8324D50, S-8324J50, S-8328E50, and 8328J50: 2.1 M
to 19.1 M
III. Attach the capacitor “CC” in parallel to RA resistance when the oscilation of the output voltage occurs.
Caluculate “CC” from the following formula:
Figure 9 Circuit example using 2SK1959
Figure 9 is a circuit example using NEC 2SK1959 MOS FET
transistor (N-channel).
For a MOS FET, an N-channel power MOS FET should be used.
Because the gate voltage and current of the external power MOS
FET are supplied from the stepped up output voltage VOUT, the MOS
FET is driven more effectively.
Depending on which MOS FET you use in your device, there is a
chance of a current overrun at power ON.
Thoroughly test all settings with your device before deciding on
which one to use. Also, try to use a MOS FET with the gate
capacitance of 300 pF or less.
Since the ON resistor of the MOS FET might affect the output
amperage as well as the efficiency, the threshold voltage should be
low. When the output voltage is as low as 2.0V the same as in the
S-8328E20, the circuit operates only when the MOS FET has the
threshold voltage lower than 2.0V.
VOUT
EXT
VOUT
-
+
(ON / OFF)
(VDD)
VSS
+
-
CC (F)=
2
π RA 20 kHz
1
DISCONTINUED
PRODUCT
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