參數(shù)資料
型號(hào): S-24C02B
廠商: Seiko Instruments Inc.
英文描述: 2Kbits CMOS 2-Wired Serial EEPROM(2K位CMOS 2線串行EEPROM)
中文描述: 2Kbits的CMOS 2 -有線串行EEPROM(2K位的CMOS 2線串行EEPROM的)
文件頁數(shù): 14/53頁
文件大?。?/td> 173K
代理商: S-24C02B
CMOS 2-WIRED SERIAL EEPROM
S-24C01B/02B/04B
Seiko Instruments Inc.
13
7.3Sequential Read
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code “1” in both
current and random read operations, following the start condition signal, it outputs the acknowledgment signal.
When 8-bit length data is output from the EEPROM, in synchronization with the SCL clock, the memory
address counter inside the EEPROM is automatically incremented at the falling edge of the SCL clock, by which
the 8th data is output.
When the master device transmits the acknowledgment signal, the next memory address data is output.
When the master device transmits the acknowledgment signal, the memory address counter inside the
EEPROM is incremented and read data in succession. This is called “Sequential Read”.
When the master device does not output an acknowledgement signal and transmits the stop condition
signal, the read operation is finished.
Data can be read in the “Sequential Read” mode in succession. When the memory address counter reaches
the last word address, it rolls over to the first memory address.
Figure 14
Sequential Read
R
E
A
D
S
T
O
P
DEVICE
ADDRES
R
/
W
ADR INC
D7
D0
A
C
K
A
C
K
A
C
K
1
D7
D0
ADR INC
A
C
K
ADR INC
SDA LINE
DATA (n)
D7
D0
D7
D0
DATA (n+1)
DATA (n+2)
DATA (n+x)
NO ACK from
Master Device
ADR INC
相關(guān)PDF資料
PDF描述
S-24C04B 4Kbits CMOS 2-Wired Serial EEPROM(4K位CMOS 2線串行EEPROM)
S-24C01B 1Kbits CMOS 2-Wired Serial EEPROM(1K位CMOS 2線串行EEPROM)
S-24C08A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
S-24C16A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
S-24H30 64 Bits Non-Volatile CMOS RAM(64位CMOS非易失性RAM)
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