參數(shù)資料
型號: S-24C02B
廠商: Seiko Instruments Inc.
英文描述: 2Kbits CMOS 2-Wired Serial EEPROM(2K位CMOS 2線串行EEPROM)
中文描述: 2Kbits的CMOS 2 -有線串行EEPROM(2K位的CMOS 2線串行EEPROM的)
文件頁數(shù): 12/53頁
文件大小: 173K
代理商: S-24C02B
CMOS 2-WIRED SERIAL EEPROM
S-24C01B/02B/04B
Seiko Instruments Inc.
11
7. Read
7.1Current Address Read
The EEPROM is capable of storing the last accessed memory address during both writing and reading. The
memory address is stored as long as the power voltage is more than the retention voltage V
AH
.
Accordingly, when the master device recognizes the position of the address pointer inside the EEPROM,
data can be read from the memory address of the current address pointer without assigning a word address.
This is called “Current Address Read”.
“Current Address Read” is explained for when the address counter inside the EEPROM is an “n” address.
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code “1”,
following the start condition signal, it outputs the acknowledgment signal. However, in the S-24C04B, page
address P0 becomes invalid, and the memory address of the current address pointer becomes valid.
Next, 8-bit length data at an “n” address is output from the EEPROM, in synchronization with the SCL clock.
The address counter is incremented at the falling edge of the SCL clock by which the 8th bit of data is output,
and the address counter goes to address n+1.
The master device does not output the acknowledgment signal and transmits the stop condition signal to
finish reading.
For recognition of the address pointer inside the EEPROM, take into consideration the following:
The memory address counter inside the EEPROM is automatically incremented for every falling edge of the SCL
clock by which the 8th bit of data is output during the time of reading. During the time of writing, upper bits of the
memory address (upper 5 bits of the word address in the S-24C01B and S-24C02B; upper 4 bits of the word
address and page address P0 in the S-24C04B) are left unchanged and are not incremented.
Figure 12
Current Address Read
S
T
A
R
T
1 0
1
0
R
E
A
D
S
T
O
P
DEVICE
ADDRES
R
/
W
M
S
B
SDA LINE
ADR INC
x
x
P0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
L
S
B
1
DATA
NO ACK from
Master Device
(P0 is ‘don’t care’ in the S-24C01B/02B)
相關(guān)PDF資料
PDF描述
S-24C04B 4Kbits CMOS 2-Wired Serial EEPROM(4K位CMOS 2線串行EEPROM)
S-24C01B 1Kbits CMOS 2-Wired Serial EEPROM(1K位CMOS 2線串行EEPROM)
S-24C08A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
S-24C16A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
S-24H30 64 Bits Non-Volatile CMOS RAM(64位CMOS非易失性RAM)
相關(guān)代理商/技術(shù)參數(shù)
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