參數(shù)資料
型號: S-24C02B
廠商: Seiko Instruments Inc.
英文描述: 2Kbits CMOS 2-Wired Serial EEPROM(2K位CMOS 2線串行EEPROM)
中文描述: 2Kbits的CMOS 2 -有線串行EEPROM(2K位的CMOS 2線串行EEPROM的)
文件頁數(shù): 11/53頁
文件大?。?/td> 173K
代理商: S-24C02B
CMOS 2-WIRED SERIAL EEPROM
S-24C01B/02B/04B
Seiko Instruments Inc.
10
In the S-24C01B or S-24C02B, the lower 3 bits of the word address are automatically incremented each
when the EEPROM receives 8-bit write data.
Even if the write data exceeds 8 bytes, the upper 5 bits at the word address remain unchanged, the lower 3 bits
are rolled over and overwritten.
In the S-24C04B, the lower 4 bits at the word address are automatically incremented each when the
EEPROM receives 8 bit write data.
Even when the write data exceeds 16 bytes, the upper 4 bits of the word address and page address P0 remain
unchanged, and the lower 4 bits are rolled over and overwritten.
6.3Acknowledgment Polling
Acknowledgment polling is used to know when the rewriting of the EEPROM is finished.
After the EEPROM receives the stop condition signal and once it starts to rewrite, all operations are prohibited.
Also, the EEPROM cannot respond to the signal transmitted by the master device.
Accordingly, the master device transmits the start condition signal and the device address read/write instruction
code to the EEPROM (namely, the slave device) to detect the response of the slave device. This allows users to
know when the rewriting of the EEPROM is finished.
That is, if the slave device does not output the acknowledgment signal, it means that the EEPROM is rewriting;
when the slave device outputs the acknowledgment signal, you can know that rewriting has been completed. It
is recommended to use read instruction “1” for the read/write instruction code transmitted by the master device.
6.4Write Protection
The S-24C01B/02B/04B are capable of protecting the memory. When the WP pin is connected to V
CC
,
writing to all memory area is prohibite in the S-24C01B, writing to 50% of the latter half of memory area is
prohibited in the S-24C02B and S-24C04B. (prohibited adress are 080h to 0FFh in the S-24C02B; 100h to 1FFh
in the S-24C04B) Even when writing is prohibited, since the controller inside the IC is operating, the response to
the signal transmitted by the master device is not available during the time of writing (t
WR
).
When the WP pin is connected to GND, the write protection becomes invalid, and writing in all memory area
becomes available. However, when there is no need for using write protection, always connect the WP pin to
GND.
Figure 11
Page Write
S
T
A
R
T
1
0 1
0
W
R
I
T
E
S
T
O
P
DEVICE
ADDRES
WORD ADDRESS (n)
DATA (n)
R
/
W
M
S
B
SDA LINE
ADR INC
x
x P0
W7W6W5W4W3W2W1W0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
L
S
B
A
C
K
A
C
K
0
D7
D0
D7
D0
ADR INC
A
C
K
ADR INC
A
C
K
DATA (n+1)
DATA (n+x)
W7 is optional in the S-24C01B.
P0 is ‘don’t care’ in the S-24C01B/02B.
相關(guān)PDF資料
PDF描述
S-24C04B 4Kbits CMOS 2-Wired Serial EEPROM(4K位CMOS 2線串行EEPROM)
S-24C01B 1Kbits CMOS 2-Wired Serial EEPROM(1K位CMOS 2線串行EEPROM)
S-24C08A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
S-24C16A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
S-24H30 64 Bits Non-Volatile CMOS RAM(64位CMOS非易失性RAM)
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