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參數(shù)資料
| 型號(hào)： | S-1172B42-E6T1U |
| 元件分類： | 固定正電壓單路輸出LDO穩(wěn)壓器 |
| 英文描述： | 4.2 V FIXED POSITIVE LDO REGULATOR, 0.1 V DROPOUT, PDSO6 |
| 封裝： | HALOGEN FREE AND LEAD FREE, HSOP-6 |
| 文件頁數(shù)： | 26/34頁 |
| 文件大?。?/td> | 478K |
| 代理商： | S-1172B42-E6T1U |
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ProASIC3 DC and Switching Characteristics
2- 106
v1.3
Advance v0.7
(continued)
In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951.
3-5
Table 3-6 Temperature and Voltage Derating Factors for Timing Delays was
updated.
3-6
Table 3-5 Package Thermal Resistivities was updated.
3-5
Table 3-14 Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings
(Advanced) and Table 3-17 Summary of Maximum and Minimum DC Input
Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were
updated.
3-17 to
3-17
Table 3-20 Summary of I/O Timing Characteristics—Software Default Settings
(Advanced) and Table 3-21 Summary of I/O Timing Characteristics—Software
Default Settings (Standard Plus) were updated.
3-20 to
3-20
Table
3-11 Different
Components
Contributing
to
Dynamic
Power
Consumption in ProASIC3 Devices was updated.
3-9
Table 3-24 I/O Output Buffer Maximum Resistances1 (Advanced) and Table 3-
25 I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated.
3-22 to
3-22
Table 3-17 Summary of Maximum and Minimum DC Input Levels Applicable to
Commercial and Industrial Conditions was updated.
3-18
Table 3-28 I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 I/O
Short Currents IOSH/IOSL (Standard Plus) were updated.
3-24 to
3-26
The note in Table 3-32 I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-27
Figure 3-33 Write Access After Write onto Same Address, Figure 3-34 Read
Access After Write onto Same Address, and Figure 3-35 Write Access After
Read onto Same Address are new.
3-82 to
3-84
Figure 3-43 Timing Diagram was updated.
3-96
Advance v0.5
(January 2006)
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
N/A
The term flow-through was changed to pass-through.
N/A
Figure 2-7 Efficient Long-Line Resources was updated.
2-7
The footnotes in Figure 2-15 Clock Input Sources Including CLKBUF,
CLKBUF_LVDS/LVPECL, and CLKINT were updated.
2-16
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 ProASIC3E CCC Options.
2-24
The "SRAM and FIFO" section was updated.
2-21
The "RESET" section was updated.
2-25
The "WCLK and RCLK" section was updated.
2-25
The "RESET" section was updated.
2-25
The "RESET" section was updated.
2-27
The "Introduction" of the "Advanced I/Os" section was updated.
2-28
Previous Version
Changes in Current Version (v1.3)
Page
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S-1172B42-U5T1U | 4.2 V FIXED POSITIVE LDO REGULATOR, 0.1 V DROPOUT, PDSO5 |
| S-1200B47-I6T2G | 4.7 V FIXED POSITIVE LDO REGULATOR, 0.19 V DROPOUT, PDSO6 |
| S-1313D11-N4T1U3 | FIXED POSITIVE LDO REGULATOR, PDSO4 |
| S-1313D17-A4T1U3 | FIXED POSITIVE LDO REGULATOR, PDSO4 |
| S-1313D17-N4T1U3 | FIXED POSITIVE LDO REGULATOR, PDSO4 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S-1172B42-U5T1G | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR |
| S-1172B43-E6T1G | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR |
| S-1172B43-U5T1G | 制造商:Seiko Instruments Inc (SII) 功能描述:LINEAR LDO REG HI 70UA IQ 1000MA IOUT |
| S-1172B44-E6T1G | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR |
| S-1172B44-U5T1G | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR |
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