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參數(shù)資料
| 型號： | RTL8201BL |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER RTL8201BL |
| 中文描述： | 瑞昱單片單端口10/100M自適應(yīng)快速以太網(wǎng)PHYCEIVER RTL8201BL |
| 文件頁數(shù)： | 5/29頁 |
| 文件大小： | 335K |
| 代理商： | RTL8201BL |
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RTL8201BL
2002-03-29
Rev.1.2
5
5. Pin Description
LI: Latched Input in power up or reset
I: Input
P: Power
I/O: Bi-directional input and output
O: Output
5.1 100 Mbps MII & PCS Interface
Symbol
TXC
Type
O
Pin No.
7
Description
Transmit Clock:
This pin provides a continuous clock as a timing reference
for TXD[3:0] and TXEN.
Transmit Enable:
The input signal indicates the presence of a valid nibble
data on TXD[3:0].
Transmit Data:
MAC will source TXD[0..3] synchronous with TXC when
TXEN is asserted.
Receive Clock:
This pin provides a continuous clock reference for RXDV
and RXD[0..3] signals. RXC is 25MHz in the 100Mbps mode and 2.5Mhz in
the 10Mbps mode.
Collision Detected:
COL is asserted high when a collision is detected on the media.
Carrier Sense:
This pin’s signal is asserted high if the media is not in IDEL state.
Receive Data Valid:
This pin’s signal is asserted high when received data is
present on the RXD[3:0] lines; the signal is deasserted at the end of the
packet. The signal is valid on the rising of the RXC.
Receive Data:
These are the four parallel receive data lines aligned on the
nibble boundaries driven synchronously to the RXC for reception by the
external physical unit (PHY).
Receive error:
if any 5B decode error occurs, such as invalid J/K, T/R,
invalid symbol, this pin will go high.
Fiber/UTP Enable:
During power on reset, this pin status is latched to
determine at which media mode to operate:
1: Fiber mode
0: UTP mode
An internal weak pull low resistor, sets this to the default of UTP mode. It is
possible to use an external 5.1K
pull high resistor to enable fiber mode.
After power on, the pin operates as the Receive Error pin.
Management Data Clock: This pin provides a clock synchronous to MDIO,
which may be asynchronous to the transmit TXC and receive RXC clocks.
The clock rate can be up to 2.5MHz.
Management Data Input/Output:
This pin provides the bi-directional
signal used to transfer management information.
TXEN
I
2
TXD[3:0]
I
3, 4, 5, 6
RXC
O
16
COL
CRS
RXDV
O
O
O
1
23
22
RXD[3:0]
O
18, 19, 20, 21
RXER/
FXEN
O/LI
24
MDC
I
25
MDIO
I/O
26
5.2 SNI (Serial Network Interface): 10Mbps only
Symbol
COL
RXD0
CRS
RXC
TXD0
TXC
TXEN
Type
O
O
O
O
I
O
I
Pin No.
1
21
23
16
6
7
2
Description
Collision Detect
Received Serial Data
Carrier Sense
Receive Clock:
Resolved from received data
Transmit Serial Data
Transmit Clock:
Generate by PHY
Transmit Enable:
For MAC to indicate transmit operation
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RTL8201BL-LF | 制造商:Realtek Semiconductor 功能描述: |
| RTL8201CP | 制造商:Realtek 功能描述:10M/100M |
| RTL8201CP-LF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER (With Auto Crossover) |
| RTL8201CP-VD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER (With Auto Crossover) |
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