參數(shù)資料
型號(hào): RTL8139C
廠商: Electronic Theatre Controls, Inc.
英文描述: REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述: 瑞昱3.3V的單芯片快速以太網(wǎng)控制器電源管理
文件頁數(shù): 30/62頁
文件大?。?/td> 648K
代理商: RTL8139C
RTL8139C(L)
2002/01/10
Rev.1.4
30
6.29 Config5: Configuration Register 5
(Offset 00D8h, R/W)
This register, unlike other Config registers, is not protected by the 93C46 Command register. Therefore, there is no need to
enable Config register write prior to writing to Config5.
Bit
7
6
R/W
-
R/W
Symbol
-
BWF
Description
Reserved
Broadcast Wakeup Frame:
0: Default value. Disable Broadcast Wakeup Frame with mask bytes
of only DID field = FF FF FF FF FF FF.
1: Enable Broadcast Wakeup Frame with mask bytes of only DID
field = FF FF FF FF FF FF.
The power-on default value of this bit is 0.
Mroadcast Wakeup Frame:
0: Default value. Disable Multicast Wakeup Frame with mask bytes
of only DID field, which is a multicast address.
1: Enable Multicast Wakeup Frame with mask bytes of only DID
field, which is a multicast address.
The power-on default value of this bit is 0.
Unicast Wakeup Frame:
0: Default value. Disable Unicast Wakeup Frame with mask bytes of
only DID field, which is its own physical address.
1: Enable Unicast Wakeup Frame with mask bytes of only DID field,
which is its own physical address.
The power-on default value of this bit is 0.
FIFO Address Pointer:
(Realtek internal use only to test FIFO SRAM)
0: (Power-on) default value. Both Rx and Tx FIFO address pointers
are updated in ascending way from 0 and upwards. The initial FIFO
address pointer is 0.
1: Both Rx and Tx FIFO address pointers are updated in descending
way from 1FFh and downwards. The initial FIFO address pointer is
1FFh.
Note: This bit does not participate in EEPROM auto-load. The FIFO
address pointers can not be reset, except initial power-on.
The power-on default value of this bit is 0.
Link Down Power Saving mode:
When cable is disconnected (Link
Down), the analog part will power down itself (PHY Tx part & part of
twister) automatically. However, the PHY Rx part and part of twister
to monitor SD signal will not, in case the cable is re-connected and
Link should be established again.
1: Disable.
0: Enable.
LANWake signal enable/disable:
1: Enable LANWake signal.
0: Disable LANWake signal.
PME_Status bit:
Always sticky/can be reset by PCI RST# and
software.
1: The PME_Status bit can be reset by PCI reset or by software.
0: The PME_Status bit can only be reset by software.
5
R/W
MWF
4
R/W
UWF
3
R/W
FIFOAddrPtr
2
R/W
LDPS
1
R/W
LANWake
0
R/W
PME_STS
Config5 register, offset D8h: (SYM_ERR register is changed to Config5, the function of SYM_ERR register is no longer
supported by RTL8139C.)
The 3 bits (bit2-0) are auto-loaded from EEPROM Config5 byte to RTL8139C Config5 register.
相關(guān)PDF資料
PDF描述
RTL8139L REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139 REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139A REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139B REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139D REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
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