參數(shù)資料
型號(hào)： RTL8139C
廠商： Electronic Theatre Controls, Inc.
英文描述： REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 瑞昱3.3V的單芯片快速以太網(wǎng)控制器電源管理
文件頁(yè)數(shù)： 14/62頁(yè)
文件大?。?/td> 648K
代理商： RTL8139C
RTL8139C(L)
2002/01/10
Rev.1.4
14
6.3 ERSR: Early Rx Status Register
(Offset 0036h, R)
Bit
R/W
7-4
-
3
R
Symbol
-
ERGood
Description
Reserved
Early Rx Good packet:
This bit is set whenever a packet is completely
received and the packet is good. This bit is cleared when writing 1 to it,
Early Rx Bad packet:
This bit is set whenever a packet is completely
received and the packet is bad. Writing 1 will clear this bit.
Early Rx OverWrite:
This bit is set when the RTL8139C(L)'s local
address pointer is equal to CAPR. In the early mode, this is different
from buffer overflow. It happens that the RTL8139C(L) detected an Rx
error and wanted to fill another packet data from the beginning address
of that error packet. Writing 1 will clear this bit.
Early Rx OK:
The power-on value is 0. It is set when the Rx byte count
of the arriving packet exceeds the Rx threshold. After the whole packet
is received, the RTL8139C(L) will set ROK or RER in ISR and clear
this bit simultaneously. Setting this bit will invoke a ROK interrupt.
2
R
ERBad
1
R
EROVW
0
R
EROK
6.4 Command Register
(Offset 0037h, R/W)
This register is used for issuing commands to the RTL8139C(L). These commands are issued by setting the corresponding bits for
the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here.
Bit
7-5
4
R/W
-
R/W
Symbol
-
RST
Description
Reserved
Reset:
Setting to 1 forces the RTL8139C(L) to a software reset state
which disables the transmitter and receiver, reinitializes the FIFOs,
resets the system buffer pointer to the initial value (Tx buffer is at
TSAD0, Rx buffer is empty). The values of IDR0-5 and MAR0-7 and
PCI configuration space will have no changes. This bit is 1 during the
reset operation, and is cleared to 0 by the RTL8139C(L) when the reset
operation is complete.
Receiver Enable:
When set to 1, and the receive state machine is idle,
the receive machine becomes active. This bit will read back as a 1
whenever the receive state machine is active. After initial power-up,
software must insure that the receiver has completely reset before
setting this bit.
Transmitter Enable:
When set to 1, and the transmit state machine is
idle, then the transmit state machine becomes active. This bit will read
back as a 1 whenever the transmit state machine is active. After initial
power-up, software must insure that the transmitter has completely reset
before setting this bit.
Reserved
Buffer Empty:
The Rx buffer is empty; There is no packet stored in the
Rx buffer ring.
3
R/W
RE
2
R/W
TE
1
0
-
R
-
BUFE
相關(guān)PDF資料
PDF描述
RTL8139L REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139 REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139A REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139B REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139D REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RTL8139C_PLUS 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:RTL8139C_Plus Specification
RTL8139CL 制造商:Realtek Semiconductor 功能描述:
RTL8139CL+ 制造商:Realtek Semiconductor 功能描述:
RTL8139D 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SINGLE-CHIP MULTI-FUNCTION 10/100Mbps ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139D(L) 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:RTL8139D(L) Specification
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