
RTL8139C(L)
2002/01/10
Rev.1.4
29
6.26 RX_ER Counter
(Offset 0072h-0073h, R)
Bit
Name
15-0
RXERCNT
Description/Usage
Default/ Attribute
h'[0000],
R
This 16-bit counter increments by 1 for each valid packet received.
It is cleared to zero by read command.
6.27 CS Configuration Register
(Offset 0074h-0075h, R/W)
Bit
Name
15
Testfun
14-10
-
9
LD
Description/Usage
Default/ Attribute
0,WO
-
1, RW
1 = Auto-neg speeds up internal timer
Reserved
Active low TPI link disable signal. When low, TPI still transmits
link pulses and TPI stays in good link state.
1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART
BEAT function is only valid in 10Mbps mode.
1 = enable jabber function. 0 = disable jabber function
Used to login force good link in 100Mbps for diagnostic purposes.
1 = DISABLE, 0 = ENABLE.
Assertion of this bit forces the disconnect function to be bypassed.
Reserved
This bit indicates the status of the connection. 1 = valid connected
link detected; 0 = disconnected link detected.
Assertion of this bit configures LED1 pin to indicate connection
status.
Reserved
Bypass Scramble
8
HEART BEAT
1, RW
7
6
JBEN
1, RW
1, RW
F_LINK_100
5
4
3
F_Connect
-
Con_status
0, RW
-
0, RO
2
Con_status_En
0, RW
1
0
-
-
PASS_SCR
0, RW
6.28 Flash Memory Read/Write Register
(Offset 00D4h-00D7h, R/W)
Bit
R/W
Symbol
31-24
R/W
MD7-MD0
Description
Flash Memory Data Bus:
These bits set and reflect the state of the
MD7 - MD0 pins, during write and read process respectively.
Reserved
Chip Select:
This bit sets the state of the ROMCSB pin.
Output Enable:
This bit sets the state of the OEB pin.
Write Enable:
This bit sets the state of the WEB pin.
Enable software access to flash memory:
0: Disable read/write access to flash memory via software.
1: Enable read/write access to flash memory via software and disable
the EEPROM access during flash memory access via software.
Flash Memory Address Bus:
These bits set the state of the MA16-0
pins.
23-21
20
19
18
17
-
-
W
W
W
W
ROMCSB
OEB
WEB
SWRWEn
16-0
W
MA16-MA0