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參數(shù)資料
| 型號： | RTL8139C_PLUS |
| 英文描述： | RTL8139C_Plus Specification |
| 中文描述： | RTL8139C_Plus規(guī)范 |
| 文件頁數(shù)： | 10/58頁 |
| 文件大?。?/td> | 616K |
| 代理商： | RTL8139C_PLUS |
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RTL8100B(L)
2001-11-9
Rev.1.41
10
5. Register Descriptions
The RTL8100B(L) provides the following set of operational registers mapped into PCI memory space or I/O space.
Offset
R/W
Tag
0000h
R/W
IDR0
ID Register 0:
ID registers 0-5 are only permitted to read/write by
4-byte access. Read access can be byte, word, or double word access.
The initial value is autoloaded from the EEPROM EthernetID field.
0001h
R/W
IDR1
ID Register 1
0002h
R/W
IDR2
ID Register 2
0003h
R/W
IDR3
ID Register 3
0004h
R/W
IDR4
ID Register 4
0005h
R/W
IDR5
ID Register 5
0006h-0007h
-
-
Reserved
0008h
R/W
MAR0
Multicast Register 0:
The MAR register 0-7 are only permitted to
read/write by 4-byte access. Read access can be byte, word, or double
word access. Driver is responsible for initializing these registers.
0009h
R/W
MAR1
Multicast Register 1
000Ah
R/W
MAR2
Multicast Register 2
000Bh
R/W
MAR3
Multicast Register 3
000Ch
R/W
MAR4
Multicast Register 4
000Dh
R/W
MAR5
Multicast Register 5
000Eh
R/W
MAR6
Multicast Register 6
000Fh
R/W
MAR7
Multicast Register 7
0010h-0013h
R/W
TSD0
Transmit Status of Descriptor 0
0014h-0017h
R/W
TSD1
Transmit Status of Descriptor 1
0018h-001Bh
R/W
TSD2
Transmit Status of Descriptor 2
001Ch-001Fh
R/W
TSD3
Transmit Status of Descriptor 3
0020h-0023h
R/W
TSAD0
Transmit Start Address of Descriptor0
0024h-0027h
R/W
TSAD1
Transmit Start Address of Descriptor1
0028h-002Bh
R/W
TSAD2
Transmit Start Address of Descriptor2
002Ch-002Fh
R/W
TSAD3
Transmit Start Address of Descriptor3
0030h-0033h
R/W
RBSTART
Receive (Rx) Buffer Start Address
0034h-0035h
R
ERBCR
Early Receive (Rx) Byte Count Register
0036h
R
ERSR
Early Rx Status Register
0037h
R/W
CR
Command Register
0038h-0039h
R/W
CAPR
Current Address of Packet Read
003Ah-003Bh
R
CBR
Current Buffer Address:
The initial value is 0000h. It reflects total
received byte-count in the Rx buffer.
003Ch-003Dh
R/W
IMR
Interrupt Mask Register
003Eh-003Fh
R/W
ISR
Interrupt Status Register
0040h-0043h
R/W
TCR
Transmit (Tx) Configuration Register
0044h-0047h
R/W
RCR
Receive (Rx) Configuration Register
0048h-004Bh
R/W
TCTR
Timer CounT Register:
This register contains a 32-bit
general-purpose timer. Writing any value to this 32-bit register will
reset the original timer and begin to count from zero.
004Ch-004Fh
R/W
MPC
Missed Packet Counter:
Indicates the number of packets discarded
due to Rx FIFO overflow. It is a 24-bit counter. After s/w reset, MPC
is cleared. Only the lower 3 bytes are valid.
When any value is written, MPC will be reset also.
0050h
R/W
9346CR
93C46 Command Register
0051h
R/W
CONFIG0
Configuration Register 0
Description
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