參數(shù)資料
型號(hào): RSLIC18
廠商: Intersil Corporation
英文描述: ()
中文描述: ()
文件頁數(shù): 4/10頁
文件大?。?/td> 115K
代理商: RSLIC18
4-4
S
ense Amplifier
The Sense amplifier is modeled with a two pole circuit. The
open loop gain is 4716 or 73dB and the open loop 3dB
bandwidth is 260Hz. The model for the Sense amplifier is
shown below. The non inverting input is indicated by (+), the
inverting input by (-) and the output by (o).
Transmit Amplifier
The Transmit amplifier is modeled with a two pole circuit.
The open loop gain is 4151 or 72dB and the open loop 3dB
bandwidth is 127Hz. The model for the Transmit amplifier is
shown below. The non inverting input is indicated by (+), the
inverting input by (-) and the output by (o).
The gains and component values used in the models were
matched to the actual device level simulations of each
amplifier. Lab measurements may vary due to component
tolerances and process variations.
Simulation Example - Resistive Load
Resistive matching is a misnomer, since the impedance
being matched is in the voice band. However, resistive
matching is the case when the device synthesizes an
impedance to match a purely resistive load. This example
will match the device to a 600
load impedance, which is the
reference impedance for most North American telephony AC
transmission specifications.
Device Impedance Synthesis
The device synthesized impedance (Z
O
) is defined as the
difference between the load impedance (Z
L
) and the sum of
the protection resistance (R
P
).
Typically the load impedance represents a combination of
loop length and phone impedance, therefore a separate term
for the loop length (ohms/foot) is not required.
The external resistor, R
S
, which programs the synthesized
impedance is calculated from the equation shown below.
The resistor value used in the application circuit will be the
standard component value nearest to the calculated value.
G
42
Simulation
The G
42
frequency response of the device is simulated
using the circuit of Figure 9.
The VRX input of the model is driven by an AC voltage
source. The differential voltage across the 600
load is
converted to single ended by the voltage controlled voltage
source with a gain of 1. A dB voltage probe was used to
measure the magnitude and a phase voltage probe was
used to measure the phase of the frequency response.
EXPECTED RESULTS
The G
42
results are predicted using the voltage divider
relationship shown below.
The magnitude of the frequency response in the voice band,
300Hz to 3400Hz, should be approximately 0dB and the
phase should be nearly 180 degrees.
G
24
Simulation
The G
24
frequency response of the device is simulated
using the circuit of Figure 10.
FIGURE 7. SENSE AMPLIFIER 2-POLE MODEL
+
-
+
-
+
-
+
-
G = 1
+
-
+
-
G = 1
611M
92K
1p
1p
G = 4716
(o)
(-)
(+)
FIGURE 8. TRANSMIT AMPLIFIER 2-POLE MODEL
+
-
+
-
+
-
+
-
G = 1
+
-
+
-
G = 1
1.25G
100K
1p
1p
G = 4151
(o)
(
-
)
(+)
Z
O
Z
L
2R
P
600
2 35
)
530
=
=
=
(EQ. 8)
R
S
400
Z
O
400
530
212k
=
×
=
×
=
(EQ. 9)
FIGURE 9. G
42
RESISTIVE LOAD SIMULATION CIRCUIT
+
-
+
-
600
470nF
G = 1
TIP
RING
VRX
VTX
-IN
VFB
RSLIC18 MODEL
35
35
212k
470nF
10M
G
42
2
Z
P
L
O
+
-------+
600
(
)
+
)
530
+
-------------–
1
=
=
=
(EQ. 10)
FIGURE 10. G
24
RESISTIVE LOAD SIMULATION CIRCUIT
+
-
+
-
G = 2
600
470nF
TIP
RING
VRX
VTX
-IN
VFB
RSLIC18 MODEL
35
35
212k
470nF
Application Note 9824
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