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參數(shù)資料
| 型號： | RMPA61810 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 衰減器 |
| 英文描述： | Single Channel 6-18 GHz 1 Watt Power Amplifier MMIC |
| 中文描述： | 6000 MHz - 18000 MHz RF/MICROWAVE WIDE BAND MEDIUM POWER AMPLIFIER |
| 封裝： | 6.55 X 2.67 MM, 0.10 MM HEIGHT, DIE-6 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 550K |
| 代理商： | RMPA61810 |
2004 Fairchild Semiconductor Corporation
RMPA61810 Rev. B
R
Application Note
Scope:
This application note briefly describes the procedure for
evaluating the Fairchild Semiconductor RMPA61810, high
efficiency 0.25μm PHEMT Single-Channel Amplifier. The
chip configuration incorporates two stages of reactively
combined amplifiers at the output preceded by an input
amplifier stage.
Carrier Assembly:
The attached drawing shows a recommended off chip bias
scheme for the RMPA61810. The MMIC is mounted on a
Cu shim or ridge, which in turn blazed to Cu-Mo-Cu, or Cu-
W, or Mo carrier with alumina 50
RF connections and off-chip DC bias components. The
drawing shows the placement of components and bond
wire connections. The following should be noted:
microstrip lines for in/out
(1) 1 mil gold bond wires are used on the carrier assembly.
(2) Use 3-1 mil gold wires about 25 mils in length for
optimum RF performance.
(3) Vg: Gate Voltage (negative) input terminal for amplifier
stages. For best results, the gate supply should have a
source resistance less than 100
.
(4) Vd: Drain Voltage (positive) input terminal for amplifier
stages.
(5) Vg and Vd on both sides of the MMIC must be biased to
insure proper operation.
(6) Bias decoupling capacitors of 0.01 μF (multilayer) and
100 pF (single layer) are used on the carrier.
(7) Close placement of external components is essential to
stability.
(8) The test fixture may require a pair of 25μF capacitor on
the drain and gate(optional) bias terminals to prevent
oscillations caused by the test fixture connections.
(9) For Laboratory testing, use good power supplies. Set
current limits on supplies to RF drive-up current level.
Keep supply wire/leads as short as possible and if
required use additional bypass capacitors at the fixture
terminals.
Figure 3. Recommended Application Schematic Circuit Diagram
DRAIN SUPPLY
(Vd = +8V)*
GATE SUPPLY (Vg)*
*Vg and Vd on both sides of the MMIC must be biased to insure proper operation.
10,000pF
100pF
100pF
10,000pF
GROUND
(Back of Chip)
Bond Wire Ls
Bond Wire Ls
MMIC CHIP
RF IN
RF OUT
L
L
L
L
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