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參數(shù)資料
| 型號： | RM7065A-400T |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 23/52頁 |
| 文件大小： | 901K |
| 代理商： | RM7065A-400T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
23
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
The most commonly used write policy is write-back, which means that a store to a cache line does
not immediately cause memory to be updated. This increases system performance by reducing bus
traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a
subsequent memory operation. Software can, however, select write-through on a per-page basis
when appropriate, such as for frame buffers. Cache protocols supported for the data cache are as
follows:
1. Uncached
Reads to addresses in a memory area identified as uncached do not access the cache. Writes to
such addresses are written directly to main memory without updating the cache.
2. Write-back
Loads and instruction fetches first search the cache, reading the next memory hierarchy level
only if the desired data is not cache resident. On data store operations, the cache is first
searched to determine if the target address is cache resident. If it is resident, the cache contents
are updated and the cache line is marked for later write-back. If the cache lookup misses, the
target line is first brought into the cache, afterwhich the write is performed as above.
3. Write-through with write allocate
Loads and instruction fetches first search the cache, reading from memory only if the desired
data is not cache resident; write-through data is never cached in the secondary cache. On data
store operations, the cache is first searched to determine if the target address is cache resident.
If it is resident, the primary cache contents are updated and main memory is written, leaving
the
write-back
bit of the cache line unchanged; no writes occur to the secondary cache. If the
cache lookup misses, the target line is first brought into the cache, afterwhich the write is
performed as above.
4. Write-through without write allocate
Loads and instruction fetches first search the cache, reading from memory only if the desired
data is not cache resident; write-through data is never cached in the secondary cache. On data
store operations, the cache is first searched to determine if the target address is cache resident.
If it is resident, the cache contents are updated and main memory is written, leaving the
write-
back
bit of the cache line unchanged; no writes occur to the secondary cache. If the cache
lookup misses, only main memory is written.
5. Fast Packet Cache (Write-back with secondary bypass)
Loads and instruction fetches first search the primary cache, reading from memory only if the
desired data is not resident; the secondary cache is not searched. On data store operations, the
primary cache is first searched to determine if the target address is resident. If it is resident,
the cache contents are updated, and the cache line marked for later write-back. If the cache
lookup misses, the target line is first brought into the cache, afterwhich the write is performed
as above.
Associated with the data cache is the
store buffer
. When the RM7065A executes a
STORE
instruction, this single-entry buffer is written with the store data while the tag comparison is
performed. If the tag matches, then the data is written into the data cache in the next cycle that the
data cache is not accessed (the next non-load cycle). The store buffer allows the RM7065A to
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