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參數(shù)資料
| 型號： | RM7065A-400T |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7065A-400T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
22
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
4.16 Cache Memory
The RM7065A contains integrated primary instruction and data caches that support single cycle
access, as well as a large unified secondary cache with a three cycle miss penalty from the primary
caches. Each primary cache has a 64-bit read path and a 128-bit write path. Both caches can be
accessed simultaneously. The primary caches provide the integer and floating-point units with an
aggregate bandwidth of 6.4 GB per second at an internal clock frequency of 400 MHz. During an
instruction or data primary cache refill, the secondary cache can provide a 64-bit datum every
cycle following the initial three cycle latency for a peak bandwidth of 3.2 GB per second.
4.17 Instruction Cache
The RM7065A has an integrated 16 KB, four-way set associative instruction cache that is virtually
indexed and physically tagged. The effective physical index eliminates the potential for virtual
aliases in the cache.
The data array portion of the instruction cache is 64 bits wide and protected by word parity while
the tag array holds a 24-bit physical address, 14 control bits, a valid bit, and a single parity bit.
By accessing 64 bits per cycle, the instruction cache is able to supply two instructions per cycle to
the superscalar dispatch unit. For signal processing, graphics, and other numerical code sequences
where a floating-point load or store and a floating-point computation instruction are being issued
together in a loop, the entire bandwidth available from the instruction cache is consumed by
instruction issue. For typical integer code mixes, where instruction dependencies and other
resource constraints restrict the level of parallelism that can be achieved, the extra instruction
cache bandwidth is used to fetch both the taken and non-taken branch paths to minimize the
overall penalty for branches.
A 32-byte (eight instruction) line size is used to maximize the communication efficiency between
the instruction cache and the secondary cache or memory system.
The RM7065A supports cache locking on a per line basis. The contents of each line of the cache
can be
locked
by setting a bit in the Tag RAM. Locking the line prevents its contents from being
overwritten by a subsequent cache miss. Refills occur only into unlocked cache lines. This
mechanism allows the programmer to lock critical code into the cache, thereby guaranteeing
deterministic behavior for the locked code sequence.
4.18 Data Cache
The RM7065A has an integrated 16 KB, four-way set associative data cache that is virtually
indexed and physically tagged. Line size is 32 bytes (8 words). The effective physical index
eliminates the potential for virtual aliases in the cache.
The data cache is non-blocking; that is, a miss in the data cache does not necessarily stall the
processor pipeline. As long as no instruction is encountered which is dependent on the data
reference which caused the miss, the pipeline continues to advance. Once there are two cache
misses outstanding, the processor stalls if it encounters another load or store instruction.
The data array portion of the data cache is 64 bits wide and protected by byte parity while the tag
array holds a 24-bit physical address, 3 control bits, a two-bit cache state field, and two parity bits.
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