參數(shù)資料
型號： RM7065A-300T
廠商： PMC-Sierra, Inc.
英文描述： RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary
中文描述： RM7065A⑩微處理器與片上二級高速緩存的數(shù)據資料的初步
文件頁數(shù)： 8/52頁
文件大?。?/td> 776K
代理商： RM7065A-300T
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
8
List of Tables
Table 1 Instruction Issue Rules .................................................................................................12
Table 2 Dual Issue Instruction Classes .....................................................................................13
Table 3 ALU Operations ............................................................................................................15
Table 4 Integer Multiply/Divide Operations ................................................................................15
Table 5 Floating Point Latencies and Repeat Rates .................................................................17
Table 6 Cache Attributes ...........................................................................................................25
Table 7 Cache Locking Control .................................................................................................26
Table 8 Penalty Cycles ..............................................................................................................26
Table 9 Watch Control Register ................................................................................................32
Table 10 Performance Counter Control .....................................................................................33
Table 11 Cause Register ...........................................................................................................35
Table 12 Interrupt Control Register ...........................................................................................35
Table 13 IPLLO Register ...........................................................................................................35
Table 14 IPLHI Register ............................................................................................................35
Table 15 Interrupt Vector Spacing .............................................................................................36
Table 16 Boot Time Mode Stream .............................................................................................37
Table 17 System Interface .........................................................................................................38
Table 18 Clock/Control Interface ...............................................................................................39
Table 19 Interrupt Interface .......................................................................................................40
Table 20 JTAG Interface ...........................................................................................................40
Table 21 Initialization Interface ..................................................................................................40
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