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參數(shù)資料
| 型號(hào)： | RM7065A-300T |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
| 中文描述： | RM7065A⑩微處理器與片上二級(jí)高速緩存的數(shù)據(jù)資料的初步 |
| 文件頁數(shù)： | 34/52頁 |
| 文件大?。?/td> | 776K |
| 代理商： | RM7065A-300T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
34
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Since the performance counter can be set up to count clock cycles, it can be used as either a second
timer, or a watchdog interrupt. A watchdog interrupt can be used as an aid in debugging system or
software
“
hangs.
”
Typically the software is setup to periodically update the count so that no
interrupt occurs. When a hang occurs the interrupt ultimately triggers, thereby breaking free from
the hang-up.
4.34 Interrupt Handling
In order to provide better real time interrupt handling, the RM7065A provides an extended set of
hardware interrupts, each of which can be separately prioritized and separately vectored.
In addition to the standard six external interrupt pins, the RM7065A provides four more interrupt
pins for a total of ten external interrupts.
As described above, the performance counter is also a hardware interrupt source using
Int[13]
.
Historically in the MIPS architecture, interrupt 7 (
Int[7]
) was used as the timer interrupt. The
RM7065A provides a separate interrupt,
Int[12]
, for this purpose, thereby releasing
Int[7]
for use
as a pure external interrupt.
All interrupts (
Int[13:0]
), the Performance Counter, and the Timer, have corresponding interrupt
mask bits,
IM[13..0]
, and interrupt pending bits,
IP[13..0]
, in the Status, Interrupt Control, and
Cause registers. The bit assignments for the Interrupt Control and Cause registers are shown in
Table 11 and Table 12. The Status register has not changed from the RM5200 Family and is not
shown.
The
IV
bit in the Cause register is the global enable bit for the enhanced interrupt features. If this
bit is clear then interrupt operation is compatible with the RM5200 Family.
In the Interrupt Control register, the interrupt vector spacing is controlled by the Spacing field as
described below. The
Interrupt Mask
field (
IM[15:8]
)
contains the interrupt mask for interrupts
eight through thirteen.
IM[15:14]
are reserved for future use.
The
Timer Enable
(
TE
) bit is used to gate the Timer Interrupt to the Cause register. If
TE
is set to
"0", the Timer Interrupt is not gated to
IP[12]
. If
TE
is set to "1", the Timer Interrupt is gated to
IP[12]
.
The setting for Mode Bit 11 is used to determine if the Timer Interrupt replaces the
External
Interrupt
(
Int[5]*
) as an input to
IP[7]
in the Cause register. If Mode Bit 11 is set to "0",
Int[5]*
is
gated to
IP[7]
. If Mode Bit 11 is set to "1", the Timer Interrupt is gated to
IP[7]
.
In order to utilize both
Int[5]*
and the internal Timer Interrupt, Mode Bit 11 must be set to "0" and
TE
must be set to "1". In this case, the Timer Interrupt will use
IP[12]
, and
Int[5]*
will use
IP[7]
.
Refer to the logic diagram in the RM7000 User Manual for more information on the interrupt
signals.
The Interrupt Control register uses
IM13
to enable the Performance Counter Control.
Priority of the interrupts is set via two new coprocessor 0 registers called Interrupt Priority Level
Lo (IPLLO) and Interrupt Priority Level Hi (IPLHI).
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