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參數(shù)資料
| 型號： | RM5261A-300-H |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 25/42頁 |
| 文件大小： | 683K |
| 代理商： | RM5261A-300-H |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
25
RM5261A Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
3.28 Interrupt Handling
The RM5261A supports a dedicated interrupt vector. When enabled by the real time executive (by
setting a bit in the Cause register), interrupts vector to a specific address that is not shared with any
of the other exception types. This capability eliminates the need to go through the normal software
routine for exception decode and dispatch, thereby lowering interrupt latency.
3.29 Standby Mode
The RM5261A provides a means to reduce the amount of power consumed by the internal core
when the CPU is not performing any useful operations. This state is known as Standby Mode.
Executing the
WAIT
instruction enables interrupts and causes the processor to enter Standby
Mode. If the
SysAD
bus is idle when the wait instruction completes the W pipe stage, the internal
processor clock stops and the pipeline is suspended. The phase lock loop, or PLL, internal timer/
counter, and the “wake up” input pins:
Int[5:0]*
,
NMI*
,
ExtReq*
,
Reset*
, and
ColdReset*
continue to operate in their normal fashion. If the
SysAD
bus is not idle when the WAIT
instruction completes the W pipe-stage, then the
WAIT
is treated as a
NOP
until the bus operation
is completed. Once the processor is in Standby, any interrupt, including the internally generated
timer interrupt, causes the processor to exit Standby mode and resume operation where it left off.
The
WAIT
instruction is typically inserted in the idle loop of the operating system or real time
executive.
3.30 JTAG Interface
The RM5261A interface supports JTAG Test Access Port (TAP) boundary scan in conformance
with the IEEE 1149.1 specification. The JTAG interface is especially helpful for checking the
integrity of the processors pin connections.
3.31 Boot-Time Options
Fundamental operational modes for the processor are initialized by the boot-time mode control
interface. This serial interface operates at a very low frequency (SysClock divided by 256). The
low frequency operation allows the initialization information to be kept in a low cost EPROM or
system interface ASIC.
Immediately after the
VccOK
signal is asserted, the processor reads a serial bit stream of 256 bits
to initialize all the fundamental operational modes. ModeClock runs continuously from the
assertion of
VccOK
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5261A-300-HI | CONNECTOR ACCESSORY |
| RM5261A-350-H | CONNECTOR ACCESSORY |
| RM5261 | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| RM5261-200-Q | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| RM5261-200-QI | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM5261A-300HI-B002 | 制造商:PMC Sierra from Components Direct 功能描述:MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHNOLOGY - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261A-300HI-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin MQFP |
| RM5261A-300J-B002 | 制造商:PMC Sierra from Components Direct 功能描述:RM5261A-300J-B002, MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHN - Trays 制造商:PMC SIERRA 功能描述:PMC SIERRA RM5261A-300J-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin LFMQFP |
| RM5270-150S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5270-200S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5271-200S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
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