- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378162 > RM5261A-300-H (PMC-Sierra, Inc.) CONNECTOR ACCESSORY PDF資料下載
參數(shù)資料
| 型號(hào)： | RM5261A-300-H |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 683K |
| 代理商： | RM5261A-300-H |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
12
RM5261A Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
3.4
Pipeline
For integer operations, loads, stores, and other non-floating-point operations, the RM5261A
implements a 5-stage integer pipeline. In addition to the integer pipeline, the RM5261A
implements an extended 7-stage pipeline for floating-point operations.
The RM5261A multiplies the input
SysClock
by 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, or 9 to produce the
pipeline clock.
Figure 3 shows the RM5261A integer pipeline. As illustrated in the figure, up to five integer
instructions can be executing simultaneously.
Figure 3 Pipeline
3.5
Register File
The RM5261A has thirty-two general purpose registers with register location 0 (r0) hard-wired to
a zero value. These registers are used for scalar integer operations and address calculation. The
register file has two read ports and one write port and is fully bypassed to minimize operation
latency in the pipeline.
ALU
3.6
The RM5261A ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder
performs address calculations in addition to arithmetic operations. The logic unit performs all
logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each
of these units is optimized to perform all operations in a single processor cycle.
Integer Multiply/Divide
3.7
The RM5261A has a dedicated integer multiply/divide unit optimized for high-speed multiply and
multiply-accumulate operations. Table 1 shows the performance of the multiply/divide unit on
each operation.
I0
I1
I2
I3
I4
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
one cycle
1I-1R:
2I:
2R:
1A:
1A:
2A-2D:
1A-2A:
1D:
2W:
Instruction cache access
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Store Align
Data cache access and load align
Data virtual to physical address translation
Register file write
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5261A-300-HI | CONNECTOR ACCESSORY |
| RM5261A-350-H | CONNECTOR ACCESSORY |
| RM5261 | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| RM5261-200-Q | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| RM5261-200-QI | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM5261A-300HI-B002 | 制造商:PMC Sierra from Components Direct 功能描述:MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHNOLOGY - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261A-300HI-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin MQFP |
| RM5261A-300J-B002 | 制造商:PMC Sierra from Components Direct 功能描述:RM5261A-300J-B002, MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHN - Trays 制造商:PMC SIERRA 功能描述:PMC SIERRA RM5261A-300J-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin LFMQFP |
| RM5270-150S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5270-200S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5271-200S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。