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參數(shù)資料
| 型號： | RM5261-200-Q |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| 中文描述： | 64-BIT, 200 MHz, MICROPROCESSOR, PQFP208 |
| 封裝： | POWER, QFP-208 |
| 文件頁數(shù)： | 11/40頁 |
| 文件大小： | 683K |
| 代理商： | RM5261-200-Q |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002241, Issue 1
11
RM5261
Microprocessor with 64-Bit System Bus Data Sheet
Released
3
Hardware Overview
The RM5261 offers a high-level of integration targeted at high-performance embedded
applications. The key elements of the RM5261 are briefly described below.
Superscalar Dispatch
3.1
The RM5261 has an asymmetric superscalar dispatch unit which allows it to issue an integer
instruction and a floating-point computation instruction simultaneously. Integer instructions
include alu, branch, load/store, and floating-point load/store, while floating-point computation
instructions include floating-point add, subtract, combined multiply-add, converts, etc. In
combination with its high-throughput fully pipelined floating-point execution unit, the superscalar
capability of the RM5261 provides unparalleled price/performance in computationally intensive
embedded applications.
CPU Registers
3.2
The RM5261 CPU has a simple user-visible state consisting of 32 general purpose registers, two
special purpose registers for integer multiplication and division, a program counter, and no
condition code bits. Figure 2 shows the user visible state.
Figure 2 CPU Registers
3.3
Integer Unit
Like the RM5260, the RM5261 implements the MIPS IV Instruction Set Architecture, and is
therefore fully upward compatible with applications that run on processors implementing the
earlier generation MIPS I-III instruction sets. Additionally, the RM5261 includes three
implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in
the embedded market place. Described in detail in a later section, these instructions are integer
multiply-accumulate and 3-operand integer multiply.
The RM5261 integer unit includes thirty-two general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous
General Purpose Registers
63
0
Multiply/Divide Registers
63
HI
63
LO
0
r1
r2
0
0
Program Counter
63
PC
r29
r30
r31
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5261-200-QI | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| RM5261-250-Q | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| RM5261-266-Q | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| RM7065 | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
| RM7065A | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM5261-225Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5261-250Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5261-250Q-C001 | 制造商:PMC Sierra from Components Direct 功能描述:RM5261-250Q-C001, MICROPROCESSOR 64-BIT 0.25 UM CMOS TECHNOL - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261-250Q-C001, Microprocessor 64-Bit 0.25 um CMOS Technology 3.3V 208-Pin PQFP |
| RM5261-266Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5261A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus |
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