- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378162 > RM5231A (PMC-Sierra, Inc.) RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary PDF資料下載
參數(shù)資料
| 型號： | RM5231A |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| 中文描述： | RM5231A⑩微處理器與32位系統(tǒng)總線的數(shù)據(jù)資料的初步 |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 595K |
| 代理商： | RM5231A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
26
RM5231A Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Immediately after the
VccOK
signal is asserted, the processor reads a serial bit stream of 256 bits
to initialize all the fundamental operational modes. ModeClock runs continuously from the
assertion of
VccOK
.
3.32 Boot-Time Modes
The boot-time serial mode stream is defined in Table 4. Bit 0 is the bit presented to the processor
as the first bit in the stream when
VccOK
is asserted. Bit 255 is the last bit transferred.
Table 4 Boot Time Mode Bit Stream
Mode
bit
0
4:1
Description
Reserved: Must be zero
Write-back data rate (W = write data transfer, x = wait
state)
0: WWWWWWWW
1: WWxWWxWWxWWx
2: WWxxWWxxWWxxWWxx
3: WxWxWxWxWxWxWxWx
4: WWxxxWWxxxWWxxxWWxxx
5: WWxxxxWWxxxxWWxxxxWWxxxx
6: WxxWxxWxxWxxWxxWxxWxxWxx
7: WWxxxxxxWWxxxxxxWWxxxxxxWWxxxxxx
8: WxxxWxxxWxxxWxxxWxxxWxxxWxxxWxxx
9-15 reserved
Pclock to SysClock Multiplier
Mode Bits 7:5 Mode Bit 20=0 Mode Bit 20=1
000 Multiply by 2 n/a
001 Multiply by 3 n/a
010 Multiply by 4 n/a
011 Multiply by 5 Multiply by 2.5
100 Multiply by 6 n/a
101 Multiply by 7 Multiply by 3.5
110 Multiply by 8 n/a
111 Multiply by 9 Multiply by 4.5
Specifies byte ordering. Logically ORed with
BigEndian input signal.
0: Little endian
1: Big endian
Non-Block Write Protocol
00: R4000 compatible
01: reserved
10: pipelined
11: write re-issue
Timer Interrupt Enable/Disable
0: Enable the timer interrupt on
Int5*
1: Disable the timer interrupt on
Int5*
Reserved: Must be zero
Output driver strength - 100% = fastest
00: 67% strength
01: 50% strength
10: 100% strength
11: 83% strength
Mode
bit
15
17:16
Description
Reserved: Must be zero
System configuration identifiers - software
visible in Config[21..20] register
7:5
19:18
Reserved: Must be zero
8
20
Select SysClock to PClock Multiply Mode
0: Integer Multipliers
1: Half-Integer Multipliers
10:9
21
Reserved: Must be one
11
22
VccIO Setting
0: VccIO = 3.3V
1: VccIO = 2.5V
Reserved: Must be zero
12
14:13
255:23
相關PDF資料 |
PDF描述 |
|---|---|
| RM5231A-250-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-300-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-300-HI | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-350-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5261A | RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| RM525A-R2 | 制造商:Black Box Corporation 功能描述:2U Wallmount Cabinet, Beige |
| RM5260-133Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5260-150Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5260-175Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5260-200Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復。