- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378162 > RM5231A (PMC-Sierra, Inc.) RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary PDF資料下載
參數(shù)資料
| 型號： | RM5231A |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| 中文描述： | RM5231A⑩微處理器與32位系統(tǒng)總線的數(shù)據(jù)資料的初步 |
| 文件頁數(shù)： | 25/40頁 |
| 文件大?。?/td> | 595K |
| 代理商： | RM5231A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
25
RM5231A Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
In write reissue mode, a write rate of one write every two bus cycles can be achieved. Pipelined
writes have the same two bus cycle write repeat rate, but can issue one additional write following
the deassertion of
WrRdy*
.
3.27 External Requests
The External Request pin,
ExtRqst*
, is asserted by the external agent when it requires mastership
of the system interface, either to perform an independent transfer or to write to the interrupt
register within the RM5231A. An independent transfer is a data transfer between two external
agents or between an external agent and memory or peripheral on the system interface. Following
the asserting of the
ExtRqst*
, the RM5231A tri-states its drivers allowing the external agent to
use the system interface buses to complete an independent transfer. The external agent is
responsible for returning mastership of the system interface to the RM5231A when it has
completed the independent transfer and does so by executing an External Null cycle.
3.28 Interrupt Handling
The RM5231A supports a dedicated interrupt vector for real time interrupt handling. When
enabled by the real time executive by setting a bit in the Cause register, interrupts vector to a
specific address which is not shared with any of the other exception types. This capability
eliminates the need to go through the normal software routine for exception decode and dispatch,
thereby lowering interrupt latency.
3.29 Standby Mode
The RM5231A provides a means to reduce the amount of power consumed by the internal core
when the CPU is not performing any useful operations. This state is known as Standby Mode.
Executing the
WAIT
instruction enables interrupts causes the processor to enter Standby Mode.
When the
WAIT
instruction completes the W pipe stage, and if the
SysAD
bus is currently idle, the
internal processor clocks stop, thereby freezing the pipeline. The phase lock loop, or PLL, internal
timer/counter, and the “wake up” input pins:
Int[5:0]*
,
NMI*
,
ExtReq*
,
Reset*
, and
ColdReset*
continue to operate in their normal fashion. If the
SysAD
bus is not idle when the
WAIT
instruction completes the W pipe-stage, then the
WAIT
is treated as a
NOP
until the bus operation
is completed. Once the processor is in Standby, any interrupt, including the internally generated
timer interrupt, causes the processor to exit Standby and resume operation where it left off. The
WAIT
instruction is typically inserted in the idle loop of the operating system or real time
executive.
3.30 JTAG Interface
The RM5231A interface supports JTAG Test Access Port (TAP) boundary scan in conformance
with the IEEE 1149.1 specification. The JTAG interface is especially helpful for checking the
integrity of the processors pin connections.
3.31 Boot-Time Options
Fundamental operational modes for the processor are initialized by the boot-time mode control
interface. This serial interface operates at a very low frequency (SysClock divided by 256). The
low frequency operation allows the initialization information to be kept in a low cost EPROM or a
system interface ASIC.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5231A-250-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-300-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-300-HI | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-350-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5261A | RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM525A-R2 | 制造商:Black Box Corporation 功能描述:2U Wallmount Cabinet, Beige |
| RM5260-133Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5260-150Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5260-175Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5260-200Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。