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| 型號(hào)： | RM5231A-350-H |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| 中文描述： | 64-BIT, 350 MHz, MICROPROCESSOR, PQFP128 |
| 封裝： | MQFP-128 |
| 文件頁數(shù)： | 22/40頁 |
| 文件大小： | 595K |
| 代理商： | RM5231A-350-H |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
22
RM5231A Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
significantly increases performance by decoupling the
SysAD
bus transfers from the instruction
execution stream.
3.21 System Interface
The system interface consists of a 32-bit Address/Data bus with 4 parity check bits and a 9-bit
command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is
capable of transferring data between the processor and memory at a peak rate of 400 MB/sec with
a 100 MHz SysClock.
Figure 6 shows a typical embedded system using the RM5231A. In this example, a bank of
DRAMs and a memory controller ASIC share the processor’s
SysAD
bus while the memory
controller provides separate ports to a boot ROM and an I/O system.
Figure 6 Typical Embedded System Block Diagram
3.22 System Address/Data Bus
The 32-bit System Address Data (
SysAD
) bus is used to transfer addresses and data between the
RM5231A and the rest of the system. It is protected with a 4-bit parity check bus (
SysADC
).
The system interface is configurable to allow easy interfacing to memory and I/O systems of
varying frequencies. The Block Write data rate, Non-blocking Write protocol, and the Output
Drive strength are programmable at Boot time via the
Mode Control
bits. The rate at which the
processor receives data is also fully controlled by the external device.
3.23 System Command Bus
The RM5231A interface has a 9-bit System Command (
SysCmd
) bus. The command bus
indicates whether the
SysAD
bus carries address or data information on a per- clock basis. If the
SysAD
carries address, then the
SysCmd
bus also indicates what type of transaction is to take
place (for example, a read or write). If the
SysAD
carries data, then the
SysCmd
bus also gives
information about the data (for example, this is the last data word transmitted, or the data contains
an error). The
SysCmd
bus is bidirectional to support both processor requests and external
requests to the RM5231A. Processor requests are initiated by the RM5231A and responded to by
an external device. External requests are issued by an external device and require the RM5231A to
respond.
RM5231A
Memory I/O
Controller
Flash/
Boot
Rom
Control
x
x
36
PCI Bus
36
8
23
Latch
DRAM
Address
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