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參數資料
| 型號： | RM5231A-350-H |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| 中文描述： | 64-BIT, 350 MHz, MICROPROCESSOR, PQFP128 |
| 封裝： | MQFP-128 |
| 文件頁數： | 17/40頁 |
| 文件大?。?/td> | 595K |
| 代理商： | RM5231A-350-H |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
17
RM5231A Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Figure 4 CP0 Registers
3.13 Virtual to Physical Address Mapping
The RM5231A provides three modes of virtual addressing:
user mode
kernel mode
supervisor mode
This mechanism is available to system software to provide a secure environment for user
processes. Bits in the CP0
Status
register determine which virtual addressing mode is used. In the
user mode, the RM5231A provides a single, uniform virtual address space of 1TB (2 GB in 32-bit
mode).
When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5 TB (4
GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of
the virtual address.
The RM5231A processor also supports a supervisor mode in which the virtual address space over
2 TB (2.5 GB in 32-bit mode), divided into three regions based on the high-order bits of the virtual
address.
When the RM5231A is configured as a 64-bit microprocessor, the virtual address space layout is
an upward compatible extension of the 32-bit virtual address space layout.
0
47
TLB
(entries protected
from TLBWR)
EntryHi
10*
EntryLo0
2*
EntryLo1
3*
PageMask
5*
Wired
6*
Random
1*
Index
0*
Status
12*
Cause
13*
EPC
14*
ErrorEPC
30*
Count
9*
Compare
11*
Context
4*
PRId
15*
Config
16*
TagHi
29*
TagLo
28*
ECC
26*
CacheErr
27*
BadVAddr
8*
LLAddr
17*
* Register number
XContext
20*
Used for memory
management
Used for exception
processing
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