參數(shù)資料
型號(hào)： RM5231A-350-H
廠商： PMC-SIERRA INC
元件分類： 微控制器/微處理器
英文描述： RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary
中文描述： 64-BIT, 350 MHz, MICROPROCESSOR, PQFP128
封裝： MQFP-128
文件頁(yè)數(shù)： 12/40頁(yè)
文件大?。?/td> 595K
代理商： RM5231A-350-H
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
12
RM5231A Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Figure 3 Pipeline
3.4
Integer Unit
The RM5231A integer unit includes thirty-two general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous
multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-
operand integer multiply/divide operations, and the program counter (PC).
The RM5231A implements the MIPS IV Instruction Set Architecture, and is therefore fully
upward compatible with applications that run on processors implementing the earlier generation
MIPS I-III instruction sets.
Register File
3.5
The RM5231A has thirty-two general purpose registers with register location 0 (r0) hard wired to
a zero value. These registers are used for scalar integer operations and address calculation. The
register file has two read ports and one write port and is fully bypassed to minimize operation
latency in the pipeline.
ALU
3.6
The RM5231A ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder
performs address calculations in addition to arithmetic operations. The logic unit performs all
logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each
of these units is optimized to perform all operations in a single processor cycle.
Integer Multiply/Divide
3.7
The RM5231A has a dedicated integer multiply/divide unit optimized for high-speed multiply and
multiply-accumulate operations. Table 1 shows the performance of the multiply/divide unit on
each operation
I0
I1
I2
I3
I4
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
one cycle
1I-1R:
2I:
2R:
1A:
1A:
2A-2A:
1A-2A:
1D:
2W:
Instruction cache access
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Store Align
Data cache access and load align
Data virtual to physical address translation
Register file write
相關(guān)PDF資料
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