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| 型號(hào)： | RK80532PC041512 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 50/86頁 |
| 文件大?。?/td> | 882K |
| 代理商： | RK80532PC041512 |
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50
Datasheet
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
Table 27. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance
Note:
The undershoot guideline limits transitions exactly as described for the AGTL signals. See
Figure 20
.
3.4.2
Ringback Specification
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. See
Figure 21
for an illustration of ringback. Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL signals.
Ringback can be simulated with or without the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See
Table 28
for the signal ringback specifications for non-AGTL signals for simulations at the
processor pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
cache at all frequencies.
2. Non-AGTL signals except PWRGOOD.
3.4.3
Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10% of the total signal swing (V
HI
–
V
LO
) above
and below its final value. A signal should be within the settling limits of its final value, when either
in its high state or low state, before it transitions again.
Overshoot/Undershoot
Magnitude (V)
Maximum Pulse Duration at
Tcase = 69 °C (ns)
AF = 0.01
AF = 0.1
AF = 1
2.38
35
3.5
0.35
2.33
60
8.0
0.8
2.28
60
18
1.8
2.23
60
41
4.1
2.18
60
60
9.0
2.13
60
60
21
2.08
60
60
60
Table 28. Signal Ringback Specifications for Non-AGTL Signal Simulation at the Processor
Pins
1
Input Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Non-AGTL Signals
2
Non-AGTL Signals
2
0
→
1
1
→
0
0
→
1
Vcmos_ref + 0.200
V
21
Vcmos_ref - 0.300
V
21
PWRGOOD
1.44
V
21
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