- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄225036 > RG82845MZ Controller Miscellaneous - Datasheet Reference PDF資料下載
參數(shù)資料
| 型號(hào)： | RG82845MZ |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 126/157頁(yè) |
| 文件大小： | 1407K |
| 代理商： | RG82845MZ |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)當(dāng)前第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
70
Datasheet
250687-002
R
3.7.24.
ESMRAMC – Extended System Mgmt RAM Control Register –
Device #0
Address Offset:
9Eh
Default Value:
38h
Access:
Read Only, Read/Write, Read/Write Clear, Lock
Size:
8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended
SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1
MByte.
Bit
Description
7
H_SMRAM_EN (H_SMRAME): Controls the SMM memory space location (i.e. above 1 MByte or
below 1 MByte) When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM
memory space is enabled. SMRAM accesses from FEDA_0000h to FEDB_FFFFh are remapped to
DRAM address 000A0000h to 000BFFFFh.
Once D_LCK is set, this bit becomes read only.
6
E_SMRAM_ERR (E_SMERR): This bit is set when host accesses the defined memory ranges in
Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit =
0. It is software’s responsibility to clear this bit. The software must write a 1 to this bit to clear it
5
SMRAM_Cache (SM_CACHE): This bit is hardwired to ‘1’.
4
SMRAM_L1_EN (SM_L1): This bit is hardwired to ‘1’.
3
SMRAM_L2_EN (SM_L2): This bit is hardwired to ‘1’.
2:1
TSEG_SZ[1-0] (T_SZ): Selects the size of the TSEG memory block if enabled. This memory is
taken from the top of DRAM space (i.e. TOM - TSEG_SZ), which is no longer claimed by the memory
controller (all accesses to this space are sent to the hub interface if TSEG_EN is set). This field
decodes as follows:
TSEG_SZ[1,0]
Description
00
(TOM-128K) to TOM
01
(TOM-256K) to TOM
10
(TOM-512K) to TOM
11
(TOM-1M) to TOM (845MP Only)
Once D_LCK is set, this bit becomes read only.
0
TSEG_EN (T_EN): Enabling of SMRAM memory (TSEG, 128 Kbytes, 256 Kbytes, 512 Kbytes or 1
Mbytes of additional SMRAM memory) for Extended SMRAM space only. When G_SMRAME =1 and
TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space.
Once D_LCK is set, this bit becomes read only.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RG82870P2 | Controller Miscellaneous - Datasheet Reference |
| RH5RE36AA-T1-FA | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RH5RE56AA-T1-FA | 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RE5RE36AA-TZ-FC | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PBCY3 |
| RE5RE36AC-TZ-FC | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PBCY3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RG82845PE S L6H5 | 制造商:Intel 功能描述:CHIPSTGMCH 82845PE HT-PBGA760 |
| RG82845PESL6Q3 | 制造商:Intel 功能描述:Chipsets |
| RG82845-SL5V7 | 制造商:Intel 功能描述:INTEL 845G GRAPHICS AND MEMORY CONTROLLER HUB(GMCH) |
| RG82845SL5YQ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel?? 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR |
| RG82845-SL63W | 制造商:Intel 功能描述:INTEL 845G GRAPHICS AND MEMORY CONTROLLER HUB(GMCH) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。