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Preliminary
5-38
RF2483
Rev A2 010904
5
M
U
Application Notes
The baseband inputs must be driven with balanced dif-
ferential signals. We suggest amplitude and phase
matching <0.5dB and <0.5°. Phase or gain imbalances
between the complementary input signals will cause
additional distortion including some second order
baseband distortion.
The common-mode voltage on the baseband inputs
should be well controlled at 1.2V. We suggest that the
common-mode DC voltage be 1.2V+0.05V. The com-
mon-mode DC voltage is used to bias the modulator;
hence, deviations from 1.2V will result in changes in
the current consumption, noise and intermodulation
performance.
The chip is designed to be driven with a single-ended
LO signal.
The GC DEC and VREF output pins should be decou-
pled to ground. We recommend a 10nF capacitor on
VREF, and a 1nF capacitor on GC DEC. The purpose
of this capacitor is to filter out low frequency noise
(20MHz) in the gain control lines, which may cause
noise on the RF signal. The capacitor on the GC DEC
line will effect the settling time response to a change in
power control voltage. A 1nF capacitor equates to
around a 200ns settling time, and a 0.5nF capacitor
equates to a 100ns settling time. There is a trade-off
between settling time and phase noise as you start to
apply gain control.
The ground lines for the LO sections, GNDLO and
GND1, are brought out of the chip independently from
the ground to the RF and modulator sections. This iso-
lates the LO signals from the RF output sections.
The GND LO pin is effectively the complementary LO
input for both the high band and low band LO signals. It
has significant amounts of LO signal flowing through it.
This is brought out as an independent ground to try to
enable the PCB board designer to isolate the LO return
from the RF output sections and general chip ground.
The RF output ports of the RF2483 consist of open col-
lector architecture and require pull up inductors to the
supply voltage. This, in conjunction with a DC blocking
capacitor provides a simple, broadband L-match net-
work as shown in the schematic diagram. A shunt
resistor is included to control the Q of the matching
network and set the modulator output power. In this
case, both outputs were designed to provide 0dBm.
An alternate output match containing a third harmonic
trap was evaluated. This circuit uses a tapped-C
matching network, whereby the shunt C provides a low
impedance path near the third harmonic frequency.
Although an additional component is required, the ben-
efit of suppressing the third harmonic distortion may
improve overall system intermodulation. This network
has been shown to provide better than 20dB of
improved suppression in high-band mode.
High Band LOHB (S11) and RFHB (S22) Parameters
(V
CC
=2.7V, V
GC
=2.0V, Band Sel=2.7V, EN=2.7V, T=+25°C)
Freq. (MHz)
S11 MAG S11 ANG S22 MAG S22 ANG
1700
0.478
-110.8
1750
0.469
-112.4
1800
0.465
-115.1
1850
0.472
-117.2
1900
0.476
-117.6
1950
0.465
-118.4
2000
0.457
-120.8
2050
0.452
-122.6
2100
0.464
-123.0
2150
0.453
-123.4
2200
0.442
-125.4
Low Band LOLB (S11) and RFLB (S22) Parameters
(V
CC
=2.7V, V
GC
=2.0V, Band Sel=0V, EN=2.7V, T=+25°C)
Freq. (MHz)
S11 MAG S11 ANG S22 MAG S22 ANG
700
0.468
-63.2
750
0.452
-67.6
800
0.437
-72.1
850
0.425
-76.6
900
0.414
-81.2
950
0.407
-85.6
1000
0.402
-89.8
0.903
0.901
0.902
0.902
0.904
0.905
0.906
0.909
0.916
0.914
0.879
-55.0
-56.2
-57.2
-58.0
-59.0
-59.6
-60.3
-60.9
-61.9
-64.0
-64.5
0.92
0.915
0.913
0.908
0.905
0.901
0.898
-9.9
-11.3
-12.6
-14.0
-15.6
-17.1
-18.8
L3
2.2 nH
R4
180
C4
100 pF
VCC
C11
2 pF
C12
1 pF
J4
RFOUT HB
C15
6 pF
C13
2 pF
J8
RFOUT LB
L4
10 nH
R6
130
C6
100 pF
VCC
Figure 1. Alternate RF output match with
third-harmonic suppression.