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16.6.1
SCFTDR Writing and TDFE Flag .................................................................... 815
16.6.2
SCFRDR Reading and RDF Flag ..................................................................... 815
16.6.3
Restriction on Direct Memory Controller Usage .............................................. 816
16.6.4
Break Detection and Processing ....................................................................... 816
16.6.5
Sending a Break Signal..................................................................................... 816
16.6.6
Receive Data Sampling Timing and Receive Margin
(Asynchronous Mode)....................................................................................... 816
16.6.7
Selection of Base Clock in Asynchronous Mode.............................................. 818
Section 17 Renesas Serial Peripheral Interface ................................................. 819
17.1
Features............................................................................................................................. 819
17.2
Input/Output Pins.............................................................................................................. 822
17.3
Register Descriptions........................................................................................................ 823
17.3.1
Control Register (SPCR) .................................................................................. 825
17.3.2
Slave Select Polarity Register (SSLP) .............................................................. 827
17.3.3
Pin Control Register (SPPCR) .......................................................................... 828
17.3.4
Status Register (SPSR) ..................................................................................... 830
17.3.5
Data Register (SPDR)....................................................................................... 833
17.3.6
Sequence Control Register (SPSCR) ................................................................ 834
17.3.7
Sequence Status Register (SPSSR) ................................................................... 836
17.3.8
Bit Rate Register (SPBR) ................................................................................. 837
17.3.9
Data Control Register (SPDCR) ....................................................................... 839
17.3.10
Clock Delay Register (SPCKD)........................................................................ 841
17.3.11
Slave Select Negation Delay Register (SSLND) .............................................. 842
17.3.12
Next-Access Delay Register (SPND) ............................................................... 843
17.3.13
Command Register (SPCMD) .......................................................................... 844
17.3.14
Buffer Control Register (SPBFCR) .................................................................. 849
17.3.15
Buffer Data Count Setting Register (SPBFDR)................................................ 851
17.4
Operation .......................................................................................................................... 852
17.4.1
Overview of Operations.................................................................................... 852
17.4.2
Pin Control........................................................................................................ 853
17.4.3
System Configuration Example ........................................................................ 854
17.4.4
Transfer Format ................................................................................................ 857
17.4.5
Data Format ...................................................................................................... 859
17.4.6
Error Detection ................................................................................................. 871
17.4.7
Initialization...................................................................................................... 876
17.4.8
SPI Operation.................................................................................................... 877
17.4.9
Error Handling .................................................................................................. 890
17.4.10
Loopback Mode ................................................................................................ 891
17.4.11
Interrupt Sources............................................................................................... 892