
R01UH0218EJ0110 Rev.1.10
Page 120 of 664
Sep 12, 2011
R32C/142 Group and R32C/145 Group
7. Clock Generator
7.2
Oscillator Stop Detection
This function detects the main clock is stopped when its oscillator stops running due to an external factor.
When the CM20 bit in the CM2 register is set to 1 (enable oscillator stop detection), an oscillator stop
detection interrupt request is generated as soon as the main clock stops. Simultaneously, the PLL
frequency synthesizer starts to self-oscillate at its own frequency. If the PLL frequency synthesizer is the
clock source for CPU clock and peripheral clock, these clocks continue running.
When an oscillator stop is detected, the following bits in the CM2 register become 1:
The CM22 bit: main clock oscillator stop detected
The CM23 bit: main clock oscillator stopped
7.2.1
How to Use Oscillator Stop Detection
The oscillator stop detection interrupt shares vectors with the watchdog timer interrupt. When using
these interrupts simultaneously, read the CM22 bit with an interrupt handler to determine if an oscillator
stop detection interrupt request has been generated.
When the main clock oscillator resumes running after an oscillator stop is detected, the PLL clock
frequency may temporarily exceed the preset value before the PLL frequency synthesizer oscillation
stabilizes. As soon as an oscillator stop is detected, the main clock oscillator should be stopped from
resuming (set the CM05 bit in the CM0 register to 1) or the divide ratios of the base clock and peripheral
clock source should be increased by a program. They can be set using bits BCD1 and BCD0 in the
CCR register and bits PM36 and PM35 in the PM3 register.
In low speed mode, when the main clock oscillator stops running, an oscillator stop detection interrupt
request is generated if the CM20 bit is set to 1 (enable oscillator stop detection). The CPU clock
remains running with a low speed clock source. Note that if the base clock is f256, which is the main
clock divided by 256, oscillator stop detection cannot be used.
The oscillator stop detection is provided to handle main clock stop caused by external factors. To stop
the main clock oscillator by a program, i.e., to enter stop mode or to set the CM05 bit to 1 (main clock
oscillator disabled), the CM20 bit in the CM2 register should be set to 0 (disable oscillator stop
detection). To enter wait mode, this bit should be also set to 0.
The oscillator stop detection functions depending on the voltage of a capacitor which is being changed.
In more concrete terms, this function detects that the oscillator is stopped when the main clock goes
lower than approximately 500 kHz. Note that if the CM22 bit is set to 0 by a program in an interrupt
handler while the frequency is around 500 kHz, a stack overflow may occur due to multiple interrupt
requests.
7.3
Base Clock
The base clock is a reference clock for the CPU clock and peripheral bus clock. The base clock after a
reset is the PLL clock divided by 6.
The base clock source is selected between the PLL clock and the low speed clocks which contain the sub
clock (fC), on-chip oscillator clock divided by 4 (fOCO4), and main clock divided by 256 (f256).
If the PLL clock is selected, it is divided by 2, 3, 4, or 6 to become the base clock. If a low speed clock is
selected, the clock itself can be the base clock.
The base clock source is set using the BCS bit in the CCR register and the divide ratio for the PLL clock is
set using bits BCD1 and BCD0. Bits CM31 and CM30 in the CM3 register select a low speed clock.