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| 型號(hào)： | R5F36S16DFB |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 32.72 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 5/55頁 |
| 文件大?。?/td> | 748K |
| 代理商： | R5F36S16DFB |
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M16C/6S1 Group
2. Central Processing Unit (CPU)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0054EJ0050 Rev.0.50
Page 13 of 52
Jun 14, 2011
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a
register bank, and there are two register banks.
Figure 2.1
CPU Registers
2.1
Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can
be split into high-order (R0H/R1H) and low-order (R0L/R1L) bits to be used separately as 8-bit data
registers.
R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers
R2R0 and R3R1, respectively.
R0H (high-order bits of R0)
b15
b8 b7
b0
R3
INTBH
USP
ISP
SB
Note:
1. These registers compose a register bank. There are two register banks.
C
D
Z
S
B
O
I
U
IPL
R2
b31
R3
R2
A1
A0
FB
b19
INTBL
b15
b0
PC
INTBH is the 4 high-order bits of the INTB register and
INTBL is the 16 low-order bits.
b19
b0
b15
b0
FLG
b15
b0
b15
b0
b7
b8
Data registers (1)
Address registers (1)
Frame base registers (1)
Program counter
Interrupt table register
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Reserved area
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
R1H (high-order bits of R1)
R0L (low-order bits of R0)
R1L (low-order bits of R1)
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