參數(shù)資料
型號： R5F3650KNFA
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 20 X 14 MM, 0.65 MM PITCH, QFP-100
文件頁數(shù)： 45/81頁
文件大?。?/td> 879K
代理商： R5F3650KNFA
63
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Figure 11-2. General Digital I/O
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
I/O,
SLEEP, and PUD are common to all ports.
11.2.1
Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register
Description for I/O-Ports” on page 80, the DDxn bits are accessed at the DDRx I/O address, the
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin
The port pins are tri-stated when reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx:
READ PORTx REGISTER
RPx:
READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O : I/O CLOCK
RDx:
READ DDRx
D
L
Q
RESET
Q
D
Q
D
CLR
PORTxn
Q
D
CLR
DDxn
PINxn
D
ATA
B
U
S
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER
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