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參數(shù)資料
| 型號(hào)： | R5F363A6DFA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 6/119頁(yè) |
| 文件大?。?/td> | 907K |
| 代理商： | R5F363A6DFA |
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R01DS0033EJ0200 Rev.2.00
Page 103 of 115
Feb 07, 2011
M16C/63 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
Switching Characteristics
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.4.5
In Wait State Setting 2
φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and Inserting 1
to 3 Recovery Cycles and Accessing External Area
Notes:
1.
Calculated according to the BCLK frequency as follows:
2.
Calculated according to the BCLK frequency as follows:
3.
This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t =
CR × ln(1 V
OL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time
of output low level is
t =
30 pF × 1 kΩ × In(1 0.2V
CC2/VCC2)
= 6.7 ns.
4.
Calculated according to the BCLK frequency as follows:
Table 5.61
Memory Expansion Mode and Microprocessor Mode (in Wait State Setting 2
φ + 3φ, 2φ +
4
φ, 3φ + 4φ, and 4φ + 5φ, and Inserting 1 to 3 Recovery Cycles and Accessing External
Area)
Symbol
Parameter
Measuring
Condition
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address output delay time
See
30
ns
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0ns
th(RD-AD)
Address output hold time (in relation to RD)
(Note 4)
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
30
ns
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0ns
td(BCLK-ALE)
ALE signal output delay time
25
ns
th(BCLK-ALE)
ALE signal output hold time
-4
ns
td(BCLK-RD)
RD signal output delay time
30
ns
th(BCLK-RD)
RD signal output hold time
0ns
td(BCLK-WR)
WR signal output delay time
30
ns
th(BCLK-WR)
WR signal output hold time
0ns
td(BCLK-DB)
Data output delay time (in relation to BCLK)
40
ns
th(BCLK-DB)
Data output hold time (in relation to BCLK) (3)
0ns
td(DB-WR)
Data output delay time (in relation to WR)
(Note 1)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
(Note 2)
ns
n
10
9
×
f
BCLK
()
------------------40 ns
[]
–
n is 3 for 2
φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
m
10
9
×
f
BCLK
()
-------------------10 ns
[]
–
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
DBi
R
C
m
10
9
×
f
BCLK
()
-------------------0 ns
[]
+
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
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相關(guān)代理商/技術(shù)參數(shù) |
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| R5F363A6DFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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