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參數(shù)資料
| 型號： | R5F2L36ACDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 24/74頁 |
| 文件大小： | 959K |
| 代理商： | R5F2L36ACDFP |
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31
2588F–AVR–06/2013
ATtiny261/461/861
Notes:
1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
6.2.7
Default Clock Source
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default
clock source setting is therefore the Internal Oscillator running at 8 MHz with longest start-up
time and an initial system clock prescaling of 8. This default setting ensures that all users can
make their desired clock source setting using an In-System or High-voltage Programmer.
For low-voltage devices (ATtiny261V/461V/861V) it should be noted that unprogramming the
CKDIV8 fuse may result in overclocking. At low voltages (below 2.7V) the devices are rated for
maximum 4 MHz operation (see Section 19.3 on page 188), but routing the clock signal from the
internal oscillator directly to the system clock line will run the device at 8 MHz.
6.3
System Clock Prescaler
The ATtiny261/461/861 system clock can be divided by setting the “CLKPR – Clock Prescale
Register” on page 32. This feature can be used to decrease power consumption when the
requirement for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
I/O, clkADC, clkCPU,
and clk
FLASH are divided by a factor as shown in Table 6-13 on page 34.
6.3.1
Switching Time
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
0
11
1K (1024)CK(2)
14CK + 4 ms
Ceramic resonator,
fast rising power
1
00
1K (1024)CK(2)
14CK + 64 ms
Ceramic resonator,
slowly rising power
1
01
16K (16384) CK
14CK
Crystal Oscillator,
BOD enabled
1
10
16K (16384) CK
14CK + 4 ms
Crystal Oscillator,
fast rising power
1
11
16K (16384) CK
14CK + 64 ms
Crystal Oscillator,
slowly rising power
Table 6-12.
Start-up Times for the Crystal Oscillator Clock Selection (Continued)
CKSEL0
SUT1:0
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(V
CC = 5.0V)
Recommended Usage
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