
R8C/38T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 435 of 730
Aug 05, 2011
20.3.3.2
Output of Start and Stop Conditions
A start condition is generated by setting the STAREQ bit in the U2SMR4 register to 1 (start).
A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to 1 (start).
A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to 1 (start).
The output procedure is as follows:
[For STSPSEL = 0]
Set the STSPSEL bit in the U2SMR4 register to 0, bits SMD2 to SMD0 in the U2MR register to 000b, and the
IICM bit in the U2SMR register to 1.
Enable SDA2 pin output using the value of the port control register.
[For STSPSEL = 1]
Set the STAREQ bit, the RSTAREQ bit, or the STPREQ bit to 1.
Set the STSPSEL bit in the U2SMR4 register to 1.
After the start/stop condition generation interrupt, set the STSPSEL bit in the U2SMR4 register to 0.
Clear the start/stop condition generation interrupt.
Table 20.12
STSPSEL Bit Functions
Function
STSPSEL = 0
STSPSEL = 1
Output of pins SCL2 and
SDA2
Output of transfer clock and data.
Output of start/stop conditions is not
automatically generated by hardware
(implemented by a program).
Output of start/stop conditions according
to bits STAREQ, RSTAREQ, and
STPREQ
Start/stop condition
interrupt request
generation timing
Detection of start/stop conditions
Completion of start/stop condition
generation