
R8C/38T-A Group
16. Timer RB2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 268 of 730
Aug 05, 2011
Figure 16.9
Example of 16-Bit Timer Operation in Programmable Wait One-Shot Generation Mode
TOPL bit in
TRBIOC register
TSTART bit in
TRBCR register
Count source
Counter input
TCSTF bit in
TRBCR register
TOSSTF bit in
TRBOCR register
INT0 input
TRBPR register
TRBSC register
TRBPR count register
TRBPRE count register
TRBPR/TRBSC
reload register
load signal
TRBPRE
reload register
load signal
TRBO output pin
Interrupt request
one-shot signal
TRBPRE register
00h
01h
00h
03h
02h
01h
00h
01h
FFh
00h
01h
00h
FFh
FFh FFh 00h
FFh
0: High one-shot pulse output, low output at timer stop and during wait period
Set to 1 by a program
Synchronized with the peripheral system clock
Falls after 2 or 3 cycles of the count source
when the source is other than an underflow of the counter
Decrement
starts
01h
03h
01h
Higher 8-bit decrement
Lower 8-bit decrement
(16-bit decrement)
00FFh
0000h
0301h
02FFh
01FFh
00FFh
0000h
0101h
When registers TRBPR, TRBSC, and TRBPRE are written
while the count is stopped, values are written to both the
reload register and counter
TRBSC
is reloaded
TRBPR
is reloaded
TRBPRE
is reloaded
TRBPRE
is reloaded
Wait time
Waveform output
Higher 8 bits in TRBSC register
Lower 8 bits in TRBPRE register
Higher 8 bits in TRBPR register
Lower 8 bits in TRBPRE register
The above diagram applies under the following conditions:
TRBPRE register = 01h, TRBPR register = 01h
TCNT16 bit in TRBMR register = 1 (16-bit timer)
TOP bit = 0 (high one-shot pulse output, low output at timer stop and during wait period),
TOCNT bit = 0 (waveform output), INOSTG bit = 1 (one-shot trigger to INT0 pin enabled),
INOSEG bit = 1 (rising edge) in TRBIOC register
TRBIE bit in TRBIR register = 1 (timer RB2 interrupt enabled)
Set to 0 by acknowledgment of an interrupt request
or by a program