
R8C/38T-A Group
18. Timer RE2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 376 of 730
Aug 05, 2011
18.6
Notes on Timer RE2
When 0 (count stops) is written to the RUN bit in the TRECR register, the count is stopped after three cycles of
the count source.
When entering module standby, set the TREOE bit in the TRECR register to 0 (TMRE2O output disabled) and set
the RUN bit to 0 (count stops), and then allow three or more cycles of the count source to elapse before setting the
MSTTRE bit in the MSTCR3 register to 1 (standby).
Switch bits OS0 to OS2 and CS3 in the TRECSR register while the TREOE bit in the TRECR register is 0
(TMRE2O output disabled).
Switching registers TREIFR and TREIER must be performed as follows:
[Real-time clock mode]
- Switch the TREIER register while the RTCF bit in the TREIFR register is 0 (no interrupt requested).
- Switch the ALIE bit in the TREIFR register while the ALIF bit in the TREIFR register is 0 (no interrupt
requested).
[Compare match timer mode]
- Switch the CMIE bit in the TREIER register while the CMIF bit in the TREIFR register is 0 (no interrupt
requested).
- Switch the OVIE bit in the TREIER register while the OVIF bit in the TREIFR register is 0 (no interrupt
requested).
When changing the CS3 bit, all of the following conditions must be met:
- The RUN bit is 0 (count stops).
- The TREOE bit is 0 (TMRE2O output disabled).
- When changing the CS3 bit from 0 to 1, the CMIF bit is 0 (no interrupt requested) and the OVIF bit is 0 (no
interrupt requested).
- When changing the CS3 bit from 1 to 0, the ALIF bit is 0 (no interrupt requested) and the RTCF bit is 0 (no
interrupt requested).
Set the RTCRST bit in the TRECR register while the RTCF/OVIF bit is 0 (no interrupt requested) and the
ALIF/CMIF bit is 0 (no interrupt requested).