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參數資料
| 型號： | R3F10031NSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FLASH, 8 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24 |
| 文件頁數： | 17/30頁 |
| 文件大?。?/td> | 229K |
| 代理商： | R3F10031NSP |
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R38F1 Group, R38F2 Group, R38F3 Group
3. Memory
REJ03B0226-0001 Rev.0.01
Nov 21, 2007
Page 24 of 28
Under development Preliminary specification
Notice: This is not a final specification. Some parametric limits are subject to change.
3.3.3
Function Set ROM Data 2 (FSROM2)
Note:
1. If the FSROM24 bit is set 0, the CKM0 bit cannot be set to 1 (LSOCO oscillation stop).
With this setting, LSOCO does not stop even in stop mode.
Address FFDBh
Bit
b7b6b5b4
b3b2
b1
b0
Symbol FSROM27 FSROM26 FSROM25 FSROM24 FSROM23 FSROM22 FSROM21 FSROM20
Bit
Symbol
Bit Name
Function
b0
FSROM20 Watchdog timer source clock
select bit
0: fLSOCO16
1: f
φSOURCE16
b1
FSROM21 Watchdog timer disable bit
0: Watchdog timer enabled
1: Watchdog timer disabled
b2
FSROM22 Watchdog timer H count
source initial value set bit
0: Initial value of WHCKSEL bit is set to 0 after reset
(watchdog timer L underflow)
1: Initial value of WHCKSEL bit is set to 1 after reset
(fLSOCO16 or f
φSOURCE16)
b3
FSROM23 STP instruction function
select bit
0: Stop mode entered at STP instruction execution
1: Internal reset occurred at STP instruction
execution
b4
FSROM24 Low-speed on-chip
oscillator control bit (1)
0: LSOCO stop disabled
1: LSOCO stop enabled
b5
FSROM25 Set to 0.
b6
FSROM26
b7
FSROM27
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