- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296941 > QL8150-6PFN144C (QUICKLOGIC CORP) FPGA, 640 CLBS, 188946 GATES, PQFP144 PDF資料下載
參數(shù)資料
| 型號： | QL8150-6PFN144C |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 188946 GATES, PQFP144 |
| 封裝： | LEAD FREE, TQFP-144 |
| 文件頁數(shù)： | 7/96頁 |
| 文件大?。?/td> | 1607K |
| 代理商： | QL8150-6PFN144C |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
15
Dedicated Clock
There is one dedicated clock in the two larger devices of the Eclipse II Family (QL8325 and QL8250). This
clock connects to the clock input of the Logic Cell and I/O registers, and RAM blocks through a hardwired
connection and is multiplexed with the programmable clock input. The dedicated clock provides a fast global
network with low skew. Users have the ability to select either the dedicated clock or the programmable clock
(Figure 13).
Figure 13: Dedicated Clock Circuitry within Logic Cell
NOTE: For more information on the clocking capabilities of Eclipse II FPGAs, see QuickLogic Application
I/O Control and Local Hi-Drives
Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK, and EN inputs of
I/Os in that bank. These input-only pins also serve as high drive inputs to a quadrant. These buffers can be
driven by the internal logic both as an I/O control or high drive. For I/O constrained designs, these pins can
be used for general purpose inputs. To provide more general purpose I/Os in the 208 PQFP package, the I/O
controls pins are not bonded out. The performance of these resources is presented in Table 9.
Table 9: I/O Control Network/Local High-Drive
Destination
TT, 25 C, 2.5 V
From Pad
From Array
I/O (far)
1.00 ns
1.14 ns
I/O (near)
0.63 ns
0.78 ns
Skew
0.37 ns
0.36 ns
Programmable Clock or
General Routing
Dedicated Clock
CLK
Logic Cell
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL8150-6PFN144I | FPGA, 640 CLBS, 188946 GATES, PQFP144 |
| QL8150-6PFN144M | FPGA, 640 CLBS, 188946 GATES, PQFP144 |
| QL8150-7PFN144C | FPGA, 640 CLBS, 188946 GATES, PQFP144 |
| QL8150-7PFN144I | FPGA, 640 CLBS, 188946 GATES, PQFP144 |
| QL8150-7PFN144M | FPGA, 640 CLBS, 188946 GATES, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL8250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250-6PQN208C-5690 | 制造商:QuickLogic Corporation 功能描述: |
| QL8250-6PQN208C-5691 | 制造商:QuickLogic Corporation 功能描述: |
| QL82SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PB516 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。