參數(shù)資料
型號(hào): QL6250E-8PS484C
廠商: QUICKLOGIC CORP
元件分類: FPGA
英文描述: FPGA, 960 CLBS, 248160 GATES, PBGA484
封裝: 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484
文件頁數(shù): 9/64頁
文件大?。?/td> 850K
代理商: QL6250E-8PS484C
2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
17
Figure 15: Required Power-Up Sequence When Using Power-Up Loading
To use the power-up loading function, designers must ensure that VCC begins to ramp within a maximum of
2 ms of VCCIO, VDED, VDED2, and VPUMP.
Voltage
V
CCIO
V
DED
V
DED2
V
PUMP
V
CC
Time
< 2 m s
V
CC
V
CC PLL
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