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| 型號(hào)： | QL6250E-8PS484C |
| 廠商： | QUICKLOGIC CORP |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 960 CLBS, 248160 GATES, PBGA484 |
| 封裝： | 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484 |
| 文件頁(yè)數(shù)： | 23/64頁(yè) |
| 文件大小： | 850K |
| 代理商： | QL6250E-8PS484C |
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2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
3
The Eclipse-E logic cell structure presented in Figure 2 is a dual register, multiplexor-based logic cell. It is
designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and
RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be
loaded from the NZ output or directly from a dedicated input.
NOTE: The input PP is not an “input” in the classical sense. It is a static input to the logic cell and selects
which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can be
connected to multiple routing channels.
The complete logic cell consists of two six-input AND gates, four two-input AND gates, seven two-to-one
multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30
(including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six
outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell
accommodates many user functions with a single level of logic delay while other architectures require two or
more levels of delay.
Figure 2: Eclipse-E Logic Cell
QS
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MS
D1
E1
NP
E2
D2
NS
F1
F3
F5
F6
F2
F4
PS
PP
MP
AZ
OZ
QZ
NZ
FZ
Q2Z
QC
QR
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