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| 型號： | QL6250E-8PQ208M |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 960 CLBS, 248160 GATES, PQFP208 |
| 封裝： | 28 X 28 MM, 3.35 MM HEIGHT, MS-028, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 56/64頁 |
| 文件大小： | 850K |
| 代理商： | QL6250E-8PQ208M |
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2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
6
The modes for the ECU block are dynamically re-programmable through the programmable logic.
NOTE: Timing numbers in Table 4 represent -8 Worst Case Commercial conditions.
Phase Locked Loop (PLL) Information
Instead of requiring extra components, designers simply need to instantiate one of the pre-configured models
(described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other
PLLs. These PLLs also have the ability to support different ranges of frequency multiplications or divisions,
driving the device at a faster or slower rate than the incoming clock frequency. When PLLs are cascaded, the
clock signal must be routed off-chip through the PLLPAD_OUT pin prior to routing into another PLL; internal
routing cannot be used for cascading PLLs.
Figure 6 illustrates a QuickLogic PLL.
Figure 6: PLL Block Diagram
Table 4: ECU Mode Select Criteria
Instruction
Operation
ECU Performancea
, -8 WCC
a. tPD, tSU and tCO do not include routing paths in/out of the ECU block.
S1
S2
S3
t
PD
t
SU
t
CO
0
Multiply
6.6 ns max
0
1
Multiply-Add
8.8 ns max
0
1
0
Accumulateb
b. Internal feedback path in ECU restricts max clk frequency to 238 MHz.
3.9 ns min
1.2 ns max
0
1
Add
3.1 ns max
1
0
Multiply (registered)c
c. B [15:0] set to zero.
9.6 ns min
1.2 ns max
1
0
1
Multiply- Add (registered)
9.6 ns min
1.2 ns max
1
0
Multiply - Accumulate
9.6 ns min
1.2 ns max
1
Add (registered)
3.9 ns min
1.2 ns max
vco
Filter
FIN
FOUT
+
-
1st Quadrant
2nd Quadrant
3rd Quadrant
4th Quadrant
Clock
Tree
Frequency Divide
Frequency Multiply
1
._.
2
._.
4
._.
4
._.
2
._.
1
.._
PLL Bypass
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