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參數(shù)資料
| 型號： | QL6250E-7PS484C |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 960 CLBS, 248160 GATES, PBGA484 |
| 封裝： | 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 40/64頁 |
| 文件大?。?/td> | 850K |
| 代理商： | QL6250E-7PS484C |
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2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
45
The rest of the PQ208 pins should be terminated at the board level in the manner presented in Table 28.
The rest of the PT280 and PS484 pins should be terminated at the board level in the manner presented in
Table 28: PQ208 Recommended Unused Pin Terminations
Signal Name
Recommended Termination
PLLOUT<x>a
a. x represents a number.
In earlier versions, the recommendation for unused PLLOUT pins was that they be connected to
VCC or GND. This was acceptable for Rev. D (and earlier) silicon, including all 0.25 m devices.
For Rev. G (and later) silicon, unused PLLOUT pins should be left unconnected. Used PLLOUT
pins will normally be connected to inputs, but can also be left unconnected. For the truth table of
PLLOUT connections, refer to
IOCTRL<y>b
b. y represents an alphabetical character.
There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is
not used. For backwards compatibility with Eclipse, it can be tied to VDED or GND. If tied to
VDED, it will draw no more than 20 A per IOCTRL pin due to the pulldown resistor.
CLK/PLLIN<x>
Any unused clock pins should be connected to VDED or GND.
PLLRST<x>
If a PLL module is not used, then the associated PLLRST<x> must be connected to VDED.
INREF<y>
If an I/O bank does not require the use of the INREF signal the pin should be connected to GND.
Table 29: PT280 and PS484 Recommended Unused Pin Terminations
Signal Name
Recommended Termination
PLLOUT<x>a
a. x represents a number.
In earlier versions, the recommendation for unused PLLOUT pins was that they be connected to
VCC or GND. This was acceptable for Rev. D (and earlier) silicon, including all 0.25 m devices.
For Rev. G (and later) silicon, unused PLLOUT pins should be left unconnected. Used PLLOUT
pins will normally be connected to inputs, but can also be left unconnected. For the truth table of
PLLOUT connections, refer to
IOCTRL<y>b
b. y represents an alphabetical character.
There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is
not used. For backwards compatibility with Eclipse, it can be tied to VCCIO(C) or GND. If tied to
VCCIO(C), it will draw no more than 20 A per IOCTRL pin due to the pulldown resistor.
CLK/PLLIN<x>
Any unused clock pins should be connected to VCCIO(C) or GND.
PLLRST<x>
If a PLL module is not used, then the associated PLLRST<x> must be connected to VCCIO(C).
INREF<y>
If an I/O bank does not require the use of the INREF signal the pin should be connected to GND.
Table 30: Recommended PLLOUT Terminations Truth Table
PLL_RESET
Recommend PLLOUT Termination
0
Must be left unconnected.
1
May be left unconnected, or connected to GND. Must not be connected to VCC.
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| QL6250E-7PS484I | FPGA, 960 CLBS, 248160 GATES, PBGA484 |
| QL6250E-7PS484M | FPGA, 960 CLBS, 248160 GATES, PBGA484 |
| QL6250E-8PQ208C | FPGA, 960 CLBS, 248160 GATES, PQFP208 |
| QL6250E-8PQ208I | FPGA, 960 CLBS, 248160 GATES, PQFP208 |
| QL6250E-8PQ208M | FPGA, 960 CLBS, 248160 GATES, PQFP208 |
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