參數(shù)資料
型號(hào)： QL6250E-7PS484C
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 960 CLBS, 248160 GATES, PBGA484
封裝： 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484
文件頁數(shù)： 11/64頁
文件大?。?/td> 850K
代理商： QL6250E-7PS484C
2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
19
NOTE: For PQ208 package: All CLK, IOCTRL, and PLLIN pins are clamped to the VDED rail. Therefore,
these pins can be driven up to VDED. All JTAG inputs are clamped to the VDED2 rail. These JTAG input
pins can only be driven up to VDED2.
NOTE: For PT280 and PS484 packages: All CLK, IOCTRL, and PLLIN pins are clamped to the VCCIO(C)
rail. Therefore, these pins can be driven up to VCCIO(C). All JTAG inputs are clamped to the VDED2 rail.
These JTAG input pins can only be driven up to VDED2.
Table 12: DC Characteristics
Symbol
Parameter
Conditions
Min
Max
Units
II
I or I/O Input Leakage Current
VI = VCCIO or GND
-10
10
A
I
OZ
3-State Output Leakage Current
V
I = VCCIO or GND
-
10
A
C
I
I/O Input Capacitancea
a. Capacitance is sample tested only. Clock pins are 12 pF maximum.
--
8
pF
CCLOCK
Clock Input Capacitance
-
8
pF
I
OS
Output Short Circuit Currentb
b. Only one output at a time. Duration should not exceed 30 seconds.
V
O = GND
VO = VCC
-15
40
-180
210
mA
I
DED
D.C. Supply Current on V
DED
-
A
I
REF
D.C. Supply Current on INREF
-
-10
10
A
IPD
Current on programmable pull-down
VCC = 1.8 V
-
50
A
ICCIO
D.C. Supply Current on VCCIO
V
CCIO = 1.8 V
VCCIO = 2.5 V
V
CCIO = 3.3 V
-
10
20
A
IPUMP
D.C. Supply Current on VPUMP
VPUMP = 3.3 V
-
A
I
PLL
D.C. Supply Current on each V
CCPLL
2.5 V
-
3
mA
ICC
D.C. Supply Currentc, d
c. For -6/-7/-8 commercial grade devices only. Maximum I
CC is 15 mA for all industrial grade devices and 25 mA for all military devices.
d. I
CC is for current drawn by VCC and VDED. If any PLLs are used, see Table 12 for current drawn by each PLL.
V
PUMP = 0 V
V
PUMP = 3.3 V
-
10
-
mA
Table 13: DC Input and Output Levelsa
a. The data provided in
Table 13 are JEDEC and PCI specifications—QuickLogic devices either meet or exceed these requirements.
For data specific to QuickLogic I/Os, see
INREF
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
V
MIN
V
MAX
V
MIN
V
MAX
V
MIN
V
MAX
V
MAX
V
MIN
mA
LVTTL
n/a
-0.3
0.8
2.2
V
CCIO + 0.3
0.4
2.4
2.0
-2.0
LVCMOS2
n/a
-0.3
0.7
1.7
V
CCIO + 0.3
0.7
1.7
2.0
-2.0
LVCMOS1
8
n/a
-0.3
0.63
1.2
VCCIO + 0.3
0.7
1.7
2.0
-2.0
GTL+
0.88
1.12
-0.3
INREF - 0.2
INREF + 0.2
V
CCIO + 0.3
0.6
n/a
40
n/a
PCI
n/a
-0.3
0.3 x V
CCIO
0.6 x V
CCIO
V
CCIO + 0.5
0.1 x
VCCIO
0.9 x
VCCIO
1.5
-0.5
SSTL2
1.15
1.35
-0.3
INREF - 0.18
INREF + 0.18
VCCIO + 0.3
0.74
1.76
7.6
-7.6
SSTL3
1.3
1.7
-0.3
INREF - 0.2
INREF + 0.2
VCCIO + 0.3
1.10
1.90
8
-8
相關(guān)PDF資料
PDF描述
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QL6250E-7PS484M FPGA, 960 CLBS, 248160 GATES, PBGA484
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QL6250E-8PQ208I FPGA, 960 CLBS, 248160 GATES, PQFP208
QL6250E-8PQ208M FPGA, 960 CLBS, 248160 GATES, PQFP208
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