參數(shù)資料
型號： QL6250E-7PS484C
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 960 CLBS, 248160 GATES, PBGA484
封裝： 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484
文件頁數(shù)： 35/64頁
文件大小： 850K
代理商： QL6250E-7PS484C
2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
40
INREF(A)
I
Differential reference voltage
The INREF is the reference voltage pin for GTL+, SSTL2,
and STTL3 standards. Follow the recommendations
provided in
Table 13 for the appropriate standard. The A
inside the parenthesis means that INREF is located in BANK
A. This pin should be tied to GND if voltage referenced
standards are not used.
PLLOUT
O
PLL output pin
Dedicated PLL output pin. Must be left unconnected if the
PLL is not driven off chip. PLLOUT pin is driven by VCCIO.
For a list of each PLLOUT pin and the VCCIO pin that
powers it see
IOCTRL(A)
I
Highdrive input
This pin provides fast RESET, SET, CLOCK, and ENABLE
access to the I/O cell flip-flops, providing fast clock-to-out
and fast I/O response times. This pin can also double as a
high-drive pin to the internal logic cells. The A inside the
parenthesis means that IOCTRL is located in Bank A. There
is an internal pulldown resistor to GND on this pin. This pin
should be tied to GND if it is not used. For backwards
compatibility with Eclipse and EclipsePlus, it can be tied to
VDED or GND. If tied to VDED, it will draw no more than
20 A per IOCTRL pin due to the pulldown resistor. The
voltage tolerance of this pin is specified by VDED.
VPUMP
I
Charge Pump Disable
This pin disables the internal charge pump for lower static
power consumption. To disable the charge pump, connect
VPUMP to 3.3 V. If the Disable Charge Pump feature is not
used, connect VPUMP to GND. For backwards compatibility
with Eclipse and EclipsePlus devices, connect VPUMP to
GND.
VDED
I
Voltage tolerance for clocks,
TDO JTAG output, and IOCTRL
This pin specifies the input voltage tolerance for CLK,
DEDCLK, PLLIN, and IOCTRL dedicated input pins, as well
as the output voltage drive TDO JTAG pins. If the PLLs are
used, VDED must be 2.5 V or 3.3 V. The legal range for
VDED is between 1.71 V and 3.6 V. For backwards
compatibility with Eclipse and EclipsePlus devices, connect
VDED to 2.5 V.
VDED2
I
Voltage tolerance for JTAG pins
(TDI, TMS, TCK, and TRSTB)
These pins specify the input voltage tolerance for the JTAG
input pins. The legal range for VDED2 is between 1.71 V and
3.6 V. These do not specify output voltage of the JTAG
output, TDO. Refer to the VDED pin section for specifying
the JTAG output voltage. VDED2 must be equal to or greater
than VDED.
VCCPLL
I
Power Supply pin for PLL
Connect to 2.5 V supply. Even if your design does not utilize
the PLLs, you must connect VCCPLL to 2.5 V.
PLL_RESET
I
PLL reset pin
If PLL_RESET is asserted, then CLKNET_OUT and
PLLPAD_OUT are reset to 0. This signal must be asserted
and then released in order for the LOCK_DETECT to work.
If a PLL module is not used, then the associated
PLLRST<x> must be connected to VDED.
Table 25: PQ208 Pin Descriptions (Continued)
Pin
Directio
n
Function
Description
相關(guān)PDF資料
PDF描述
QL6250E-7PS484I FPGA, 960 CLBS, 248160 GATES, PBGA484
QL6250E-7PS484M FPGA, 960 CLBS, 248160 GATES, PBGA484
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QL6250E-8PQ208M FPGA, 960 CLBS, 248160 GATES, PQFP208
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