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參數(shù)資料
| 型號： | QL5840-66CPS484M |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封裝： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件頁數(shù)： | 9/80頁 |
| 文件大?。?/td> | 1125K |
| 代理商： | QL5840-66CPS484M |
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2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
17
For registered control operation, the array logic drives the D input of the OE cell register which in turn drives
the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered
signal to be driven to the three-state control.
When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register to
be used for registered feedback into the logic array.
I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular
routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/O's. The
CLK and RESET signals share common lines, while the clock enables for each register can be independently
controlled. I/O interface support is programmable on a per bank basis.
The two larger QL58x0 devices contain eight I/O banks. Figure 9 illustrates the I/O bank configurations for
QL5840. The two smaller QL58x0 devices contain two I/O banks per device. Figure 10 illustrates the I/O
bank configurations for QL5820 and QL5810.
Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply
inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to
which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and
INREF can be shared within the same bank (e.g., PCI and LVTTL). In the case of the QL5820 and QL5810,
only one voltage-referenced standard can be used. The two I/O banks, A and B, share the INREF pin.
Figure 9: Multiple I/O Banks on QL5840
Embedded RAM Blocks
PLL
Fabric
Embeded Computational Units
Embedded RAM Blocks
PLL
VCCIO(F)
INREF(F)
VCCIO(E)
INREF(E)
VCCIO(D)
INREF(D)
VCCIO(C)
INREF (C)
INREF(B)
VCCIO(B)
INREF(A)
VCCIO(A)
INREF(H)
VCCIO(H)
INREF(G)
VCCIO(G)
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