- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄269904 > QL5840-66CPS484M (QUICKLOGIC CORP) PCI BUS CONTROLLER, PBGA484 PDF資料下載
參數(shù)資料
| 型號： | QL5840-66CPS484M |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封裝： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件頁數(shù)： | 2/80頁 |
| 文件大小： | 1125K |
| 代理商： | QL5840-66CPS484M |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
10
Figure 4: 2,304-bit RAM Module
The number of RAM modules varies from 4 to 24 blocks for a total of 9.2 K to 55.3 K bits of RAM. Using
the two “mode” pins, designers can configure each module into 128 x 18 and 256 x 9. The blocks are also
easily cascadable to increase their effective width and/or depth (see Figure 5
).
Figure 5: Cascaded RAM Modules
The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ
and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE
ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths
of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some
higher order data or address lines may not be used.
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts
as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for
asynchronous READ operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by
connecting corresponding address lines together and dividing the words between modules.
A similar technique can be used to create depths greater than 256 words. In this case address signals higher
than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs
are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.
The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with
data from an external PROM (typically for ROM functions).
MODE[1:0]
WA[7:0]
WD[17:0]
WE
WCLK
ASYNCRD
RA[7:0]
RD[17:0]
RE
RCLK
WDATA
RDATA
WADDR
WDATA
RADDR
RAM
Module
(2,304 bits)
RAM
Module
(2,304 bits)
相關PDF資料 |
PDF描述 |
|---|---|
| QF80C154 | 8-BIT, 12 MHz, MICROCONTROLLER, PQFP44 |
| QJ80C32-1 | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| QJ80C32 | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| QP80C51FXXX | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP40 |
| QV83C154XXX | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| QL62506PB516C | 制造商:QUICK LOG 功能描述:New |
| QL6325PQ208 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| QL6325PT280 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| QL63D5SA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:InGaAlP Laser Diode |
| QL63F5SA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:InGaAlP Laser Diode |
發(fā)布緊急采購，3分鐘左右您將得到回復。