參數(shù)資料
型號： QL5840-66CPS484M
廠商： QUICKLOGIC CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA484
封裝： 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAJ-1, BGA-484
文件頁數(shù)： 1/80頁
文件大小： 1125K
代理商： QL5840-66CPS484M
2006 QuickLogic Corporation
1
Device Highlights
High Performance PCI Controller
33/66 MHz 32-bit PCI Target
Zero-wait state PCI Target provides up to
264 MBps transfer rates
Target interface supports retry, disconnect
with/without data transfer, and target abort
Fully programmable back-end interface
Independent PCI bus (33/66 MHz) and local bus
(up to 160 MHz) clocks
Fully customizable PCI Configuration Space
Configurable FIFOs with depths up to 256 words
Reference design with driver code
(Win 95/98/2000/NT 4.0) available
PCI v2.3 compliant
Supports Type 0 configuration cycles
3.3 V PCI signaling
1.8 V supply voltage
484-ball PBGA, 280-ball LFBGA, 208-pin PQFP,
196-ball TFBGA, and 144-pin TQFP packages
Unlimited/Continuous Burst Transfers supported
Extendable PCI Functionality
Support for Configuration Space from
0
× 40 to 0 × 3FF
PCI v2.3 Power Management Spec. compatible
PCI v2.3 Vital Product Data (VPD) configuration
support
Flexible Programmable Logic
Up to 1,478 logic cells
Up to 50,688 RAM bits
Up to 264 I/O pins
All back-end interface and glue-logic can be
implemented on chip
Two 32-bit busses interface between the PCI
Controller and the Programmable Logic
Up to twenty-two 2,304 bit dual-port high
performance SRAM blocks
Up to 3,748 flip-flops available
Figure 1: QL58x0 Block Diagram
PCI Bus
PCI Bus 33/66 MHz/32 bits (data and
address)
Target
Controller
160 MHz
FIFOs
Config.
Space
High Speed
Logic Cells
High Speed
Data Path
Programmable
Logic
32-bit Interface
PCI Controller
264 User I/O
33/66 MHz/32-bit PCI Target with Embedded Programmable
Logic, Embedded Computational Units, and Dual Port SRAM
QL58x0 Enhanced QuickPCI
Target Family Data Sheet
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