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參數(shù)資料
| 型號(hào)： | QL5064-33BPS484I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封裝： | PLASTIC, BGA-484 |
| 文件頁數(shù)： | 23/45頁 |
| 文件大?。?/td> | 635K |
| 代理商： | QL5064-33BPS484I |
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2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
3
Architecture Overview
The QL5064 device in the QuickLogic QuickPCI ESP (Embedded Standard Products) family provides a
complete and customizable PCI interface solution combined with 74,000 system gates of programmable logic.
This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the
maximum possible PCI bus bandwidth.
The programmable logic portion of the device is built from 792 QuickLogic Logic Cells, and 11 QuickLogic
Dual-Port RAM Blocks. The configurable RAM blocks can each operate in 64x18, 128x9, 256x4, or 512x2
mode. These dual-port RAM blocks can be cascaded to achieve deeper or wider configurations. They can also
be combined with logic cells to form FIFOs. See RAM Module Features on page 13 for more information.
The QL5064 device includes a complete pre-designed PCI Initiator/Target interface offering full burst mode
transfers at 32 or 64 bits per clock cycle. At 66 MHz, this device offers support for 533 Mbytes/sec data
transfer rates (66.6 MHz * 8 bytes per transfer). At the maximum speed of 75 MHz (exceeding the current
maximum speed specification for PCI), the QL5064 device can achieve 600 Mbytes/sec data transfer rates.
The PCI interface is configured via internal programmable configuration bits, so no external EEPROM or
memory is needed.
The QL5064 device meets PCI 2.2 electrical and timing specifications and has been fully hardware-tested. The
QL5064 device features 3.3-volt operation with multi-volt compatible I/Os. Thus it can easily operate in
3.3-volt only systems, as well as mixed 3.3 volt/5 volt system. It can be placed on a universal signaling PCI
board.
A wide range of additional features complements the QL5064 device. The FPGA side of the device is 5 volt
and 3.3-volt PCI-compliant and is capable of implementing FIFOs at 160 MHz, and counters at over 250 MHz.
I/O pins provide individually controlled output enables, dedicated input/feedback registers, and full JTAG
capability for boundary scan and test. In addition, the QL5064 device provides the benefits of non-volatility,
high design security, immediate functionality on power-up, and a self-contained single chip solution.
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