參數(shù)資料
型號(hào)： QL5064-33BPS484I
廠商： QUICKLOGIC CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA484
封裝： PLASTIC, BGA-484
文件頁(yè)數(shù)： 2/45頁(yè)
文件大?。?/td> 635K
代理商： QL5064-33BPS484I
2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
10
Figure 7: DataOUT and Control Bus Description
Control_DATA Bus Description
The Control_DATA bus is the heart of the control circuitry for the PCI interface. The intent of this bus is to
provide access to all of the control structures necessary for a microprocessor interfaced to the QL5064 device
to be able to marshal all PCI operations. The Control_DATA bus, like the DataIN and DataOUT buses, is
synchronous to user_clk, and can be written or read on every clock. This is a bi-directional bus that offers read
and write access at 64-bits. In addition to all control structures, this bus is designed to access all of the six FIFOs.
Fifo 0
Transmit
Control
Bus
Interface
data_out
Lane
Shifter
and
Construction
Fifo 1
Transmit
Target
Read
Fifo
To Master
Controller
To Target
Controller
0
1
0
1
0
1
0
1
0
1
0
1
WR
0
1
0
1
0
1
(cntl_addr == 0xc0 ) * ctrl_cs
(cntl_addr == 0xc8 ) * ctrl_cs
(cntl_addr == 0xf8) * ctrl_cs
cntl_data[63:0]
byte_lane [7:0]
data_out_h [63:0]
data_out_BEh[7:0]
cntl_data_out [63:0]
cntl_data_in [63:0]
data_out [63:0]
data_outDES[1:0]
data_outCS
user_clk
data_out_BE[7:0]
data_out_byte_sel[2:0]
fpga_reset
user_clk
FPGA
PCI Core
cntl_wrt_nrd
cntl_be[7:0]
cntl_addr [7:3]
cntl_cs
2
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