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參數(shù)資料
| 型號： | QL5064-33BPS484I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封裝： | PLASTIC, BGA-484 |
| 文件頁數(shù)： | 11/45頁 |
| 文件大?。?/td> | 635K |
| 代理商： | QL5064-33BPS484I |
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2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
19
Interrupt Control
interrupt_i
O
Active High and level sensitive. When active and not masked, asserts a PCI
interrupt.
interrupt_o
I
Active High. Indicates an interrupt is pending for the FPGA to service.
Master Arbitration Control
fpga_loc_sel[1:0]
O
FPGA arbitration select. If the FPGA has control of the master-modeling
arbitration, these bits determine which DMA channel should initiate a DMA
transfer after the next arbitration cycle. Has relationship to pci_clk.
00 => Receive channel 1 has access to the bus
01 => Receive channel 0 has access to the bus
10 => Transmit channel 1 has access to the bus
11 => Transmit channel 0 has access to the bus
fpga_bus_req[3:0]
I
Active High. Master request status. Indicates that the respective master has need
to access the PCI bus. Has relationship to pci_clk.
fpga_bus_req[0] = receive channel 1
fpga_bus_req[1] = receive channel 0
fpga_bus_req[2] = transmit channel 1
fpga_bus_req[3] = transmit channel 0
a. I = Input from PCI to FPGA
O = Output from FPGA to PCI
Table 2: PCI Back-End Interface Signals (Continued)
Symbol
I/Oa
Description
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